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Speedgoat - HDL Coder Integration Packages

FPGAs are ideal for applications such as rapid control prototyping (RCP), hardware-in-the-loop (HIL) plant simulation, high-frequency signal acquisition and generation, and signal processing algorithms, to name just a few. Users can achieve fast, closed-loop sample rates given the parallel nature of FPGAs. Simulink Real-Time and HDL Coder, together with Speedgoat real-time systems, create a complete and seamless integrated real-time software and hardware environment for RCP and HIL simulation. Simulink Real-Time provides a high-performance, host-target prototyping environment that enables users to connect Simulink®/Simscape models to physical systems running C code on a CPU and HDL code on a FPGA. Speedgoat offers a wide range of optimized hardware sufficiently equipped with high-speed analog and digital inputs and outputs. Running Simulink designs on Speedgoat FPGA I/O modules is fast and easy and no VHDL knowledge is required. With HDL coder integration packages (HCIP), users can:

  • Automatically generate HDL code and synthesize floating-point or fixed-point Simulink models
  • Automatically build and download real-time applications to the FPGA I/O module installed in a Speedgoat target machine, or operating on a stand-alone carrier
  • Run the application in real-time with the click of a button, log data, and monitor and define parameters.

Introduction

The HCIP enables seamless integration of Speedgoat I/O modules into the HDL Workflow Advisor (HDLWA) and allows users to execute Simulink designs on programmable FPGA I/O modules using automatic HDL Code generation. This Workflow provides some basic hints on using the HDL Coder functionality in combination with Speedgoat-programmable FPGA I/O Modules and Xilinx® Vivado® Design Suite. For more information, refer also to the MathWorks help documentation:

The subsequent sections describe the various Simulink blocks (Configuration Blocks and User Blocks), the supported Interfaces and a selection of Examples to get started with your I/O module. Additional PDF documentation is available in your specific HCIP.

Download

Download the latest HCIP from the downloads section of the Speedgoat Customer Portal. If the HCIP is not available, please contact Speedgoat support.

Common Use Cases

The following use cases and corresponding models are provided to help you get started. The examples selected contain links to the interfaces used.

Configuring and monitoring FPGA signals and interrupt generation Interfacing analog input and output signals Bi-directional data streaming (FPGA <-> CPU) High-speed data logging using on-board RAM High-speed intermodule communication

Examples

To test the HDL interface functionality, dedicated examples are included in the archive file to download.

Your I/O module comes with a number of examples to show the module's basic functionality. These models serve as a springboard for further development and include the basic settings required to successfully create more complex models for compilation using HDL Coder. The individual models are presented in more detail in the subsequent sections.

The models are all color coded. The green colored subsystem is the part of the model which is compiled using HDL Coder and runs on the FPGA. Start the HDL Workflow Advisor by right clicking on the green subsystem. The blue blocks surrounding the green subsystem are interfaces to the processor section of the model or to I/O "real-world" pins. The interrupt subsystem has been given another color (magenta), as its functionality is asynchronous to both the processor and FPGA.