Best Practice — Best practices for the HDL Coder workflow with Simulink-programmable
FPGA I/O modules.
The following best practices are intended to help you avoid common errors and get
your design running as fast as possible.
You can place the generated FPGA subsystem in a referenced model. Ensure Underspecified initialization detection is set to
Classic in the Data
Validity section of the model configuration parameters. This setting
must be applied in the top model and in the referenced model so that the FPGA driver
blocks will execute in the correct order on the target machine.
Two-Stage Synchronization of Digital Inputs
Asynchronous digital input signals can cause undefined logic states if not
synchronized properly. Place a delay of 2 clock ticks directly after each digital
input in order to synchronize the external signal and avoid meta stability.
Refer to one of the following models for examples. Note that for the IO33x-21, the
delay is located within the For Each Subsystem.
Concurrent Task Execution on CPU
Avoid running multiple driver blocks which access the same FPGA I/O module in
concurrently executed tasks on multiple CPU cores. This will prevent simultaneous
access to the same hardware resource, which can lead to unexpected behavior.
Accelerated Bitstream Generation
Enable IP caching in the Create Project step of the HDL Coder Workflow Advisor to
speed up the synthesis time of your design. The synthesis tool will use the IP cache
of the reference design to reduce the synthesis time: IP Caching for Faster Reference Design Synthesis.
Use design checkpoints to speed up the build time of your bitstream. Vivado can
use design checkpoints from a previous build to generate a bitstream faster,
providing only a few changes have been made to the design. This option can be
enabled in the Build FPGA Bitstream task of the Workflow Advisor: HDL Workflow Advisor Tasks: Build FPGA Bitstream.
FPGA and CPU Synchronization
You can use the Interrupt Interface to
synchronize the CPU model with the FPGA clock. By default, the user model on the
FPGA is only enabled when the model execution on the CPU starts. You must run the
FPGA in free-running mode if you are using interrupts generated on the FPGA to
trigger the model execution on the CPU. Disable the Run FPGA
only when target application runs option in the IO3xx Setup block.
The block is located within the green FPGA subsystem of the generated Simulink