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CONTENTS

Speedgoat IO334 Aurora Example

Speedgoat IO334 Aurora Example — Example showcasing the use of the Aurora Send Receive utility block.

Model Name

The model is called IO334_aurora.slx.

Supported Modules

  • IO334-325k-32

Required Toolboxes

The list of basic software requirements are provided in the prerequisites section of the Getting Started page.

Interfaces

The IO334 Aurora example uses the following interfaces:

User Blocks

The example uses the following user blocks:

Example

To test the HDL interface functionality, dedicated examples are included in the downloaded archive file. To open the examples, navigate to the corresponding folder. Note that the examples only test I/O channels for which the loopback test method is possible. The terminal board provided must be wired as described. Examples do not test I/O channels that require external hardware (for some examples a function generator or an oscilloscope is required), but running this example will still provide sufficient confirmation of the correct setup of this implementation. The examples only test interface channels which are provided by the base functionality of the I/O module. Please note that the examples provided have been color coded. The green colored subsystem (FPGA domain) is the part of the model which is actually compiled using HDL Coder and ultimately runs on the FPGA. The FPGA domain usually has a sample frequency in the range of 100 MHz and is set in the HDL Workflow Advisor (FPGA Synthesis Software Settings). The blue blocks (CPU domain) which surround the green subsystem are interfaces to the processor section of the model. The CPU domain usually has a sample frequency in the range of 1 kHz. The interrupt subsystem has been given another color (magenta), as its functionality is asynchronous to both the processor and FPGA. The interrupt source can be selected in the generated model in the Interrupt Setup block once the model has been run through the HDL Coder Workflow Advisor.

This example demonstrates the use of the Aurora Send Receive block to connect two parts of a model through a low-latency Aurora link. For simplicity, both parts run on the same IO334 in this example. The same approach can be used to interconnect a partitioned model running on multiple FPGA I/O modules.

Open the example model by navigating to the folder containing the "*.slx" model file and double clicking the file. If the example is provided as a Simulink Project, navigate to the corresponding example folder and extract the Simulink project zip file. Then double-click the "*.prj" icon to open the project. After opening the project, open the model by double clicking the "*.slx" file. The model is shown as follows:

The DUT_Aurora subsystem is shown in the following graph. The subsystem in the top left corner contains a sine wave generator. Beneath it there is a subsystem with a first order low pass filter. Both subsystems are running at a sample rate of 1 μs. The sine wave generator and filter subsystems are connected through the two Aurora Send Receive blocks on the right side and the physical loop back wiring of the SFP cages (according to the test wiring).The AXI Stream interface for Aurora communication is implemented at the target frequency of 100 MHz. The original and filtered sine waves are connected to PCIe registers so that they are accessible from the CPU for data logging. 50 samples are packed into one frame using tapped unit delays. One frame of 50 samples is read by the CPU every CPU sample step. The CPU runs at a sample step size of 50 μs.

Note that global delay balancing is disabled for this model to avoid delay balancing registers being inserted between the Aurora Send Receive blocks and the AXI interface. We suggest enabling delay balancing locally for specific subsystems; for example, the sine wave generator and low pass filter.

The model comes with different settings for desktop simulation, HDL code generation and real-time simulation on the target machine. Use the Configure Model block to switch between the different configurations easily. Ensure signal logging is set to frame-based mode before running any simulations. Use the Configuration block to simultaneously set all File Log blocks to frame-based mode.

Test Wiring

Use the following test wiring to ensure the example provided functions correctly.

From IO334-32To IO334-32Tested Functionality
SFP 1SFP 2Aurora master/slave stream 1 and 2.

Running HDL Workflow Advisor

Before the example can be deployed and run on the real-time target machine, you will need to run through the HDL Coder Workflow Advisor steps to actually generate HDL code and a FPGA bitstream using HDL Coder (FPGA Synthesis Software Settings).

New: Reference design parameters, set at step 1.2 now control which interfaces will be available to target in step 1.3 of the workflow. This has reduced the total number of reference designs, and the list of interfaces available. Please remember to select the front plug-in and rear plug-in setting that is appropriate for your module, as well as the Aurora settings that should be used for your model (if applicable). These additional reference design parameter settings are further described in the interface sections for which they are relevant.

New: Prior to running the workflow advisor, be sure to double click the Select Module block in the demo model. If one or more of your modules support the model (due to available interface compatibility), a pop-up will display prompting you to select the module you would like to target. If only a single module is installed, and providing it is compatible, it will be automatically selected when the box is double clicked.

Upon completion, a newly generated model containing the Simulink Real-Time interface subsystem appears. At first sight, this subsystem resembles the FPGA subsystem. However, inside, the Simulink algorithm has been removed and replaced with blocks that the real-time application will use to communicate with the FPGA during simulation execution. The newly generated model is now ready to be deployed to a real-time target machine. To download the FPGA bitstream and the Simulink model to the target, click the Build Model button on the Simulink Editor toolbar. The real-time application loads on the Speedgoat target machine and the FPGA algorithm bitstream loads on the FPGA. If you are using I/O lines, check that you have connected the lines to the external hardware under test. Please note that some example models do have Global Delay Balancing intentionally disabled. If an error is displayed about delay balancing in step 2.3 of the HDL Coder Workflow Advisor, it can be safely ignored by checking the Ignore warnings checkbox.

Real-Time Simulation Outputs

The simulation results will be available in the Simulation Data Inspector once the simulation has completed on the target machine. The following screen shot shows the sine wave signals initially generated with a frequency of 10, 20 and 30 kHz. The filtered and looped-back signals are shown below. Ensure signal logging is set to frame-based mode if the simulation results appear different. Also ensure that you have applied the correct loop back wiring as described above.