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Speedgoat IO334-21 HIL Pre-Built Example

Speedgoat IO334-21 HIL Pre-Built Example — Pre-built example ready to be deployed to the hardware showcasing the analog input and analog output interface and FPGA Code Module functionality such as PWM capture (CAP), Quadrature encoding (QAE) and Interrupts

Model Name

The model is called prebuilt_IO334_hil_hdlc_slrt.slx.

Supported Modules

  • IO334-325k

Required Toolboxes

  • The list of basic software requirements are provided in the prerequisites section of the Getting Started page.

    Note: this is a pre-built example model and is ready to be deployed on the hardware. This example does not require the HDL Coder toolbox or the Xilinx Vivado Design suite.

User Blocks

The example does not utilize any user blocks. Configuration and Utility blocks for configuring the Code Module functionality, such as PWM capture and Quadrature encoding, are included in the model.

Example

To test the HDL interface functionality, dedicated examples are included in the downloaded archive file. To open the examples, navigate to the corresponding folder. Note that the examples only test I/O channels for which the loopback test method is possible. The terminal board provided must be wired as described. Examples do not test I/O channels that require external hardware (for some examples a function generator or an oscilloscope is required), but running this example will still provide sufficient confirmation of the correct setup of this implementation. The examples only test interface channels which are provided by the base functionality of the I/O module. Please note that the examples provided have been color coded. The green colored subsystem (FPGA domain) is the part of the model which is actually compiled using HDL Coder and ultimately runs on the FPGA. The FPGA domain usually has a sample frequency in the range of 100 MHz and is set in the HDL Workflow Advisor (FPGA Synthesis Software Settings). The blue blocks (CPU domain) which surround the green subsystem are interfaces to the processor section of the model. The CPU domain usually has a sample frequency in the range of 1 kHz. The interrupt subsystem has been given another color (magenta), as its functionality is asynchronous to both the processor and FPGA. The interrupt source can be selected in the generated model in the Interrupt Setup block once the model has been run through the HDL Coder Workflow Advisor.

Open the example model by navigating to the folder containing the "*.slx" model file and double clicking the file. If the example is provided as a Simulink Project, navigate to the corresponding example folder and extract the Simulink project zip file. Then double-click the "*.prj" icon to open the project. After opening the project, open the model by double clicking the "*.slx" file. The model is shown as follows:

Test Wiring RJ45-to BNC Adapter

Use the following test wiring to ensure the correct functionality of the example provided.

From RJ45 JackTo RJ45 JackTested Functionality
AO 1:4AI 1:4AO channel 1/2/3/4 to AI channel 1/2/3/4
AO 5:8AI 5:8AO channel 5/6/7/8 to AI channel 5/6/7/8
AO 9:12AI 9:12AO channel 9/10/11/12 to AI channel 9/10/11/12
AO 13:16AI 13:16AO channel 13/14/15/16 to AI channel 13/14/15/16

Test Wiring IO334-21 Rear Plug-in

From PinTo PinTested Functionality
01 10CAP - channel 1 - GPO (output only) channel 1
03 12 CAP - channel 2 - GPO (output only) channel 3
0514CAP - channel 3 - GPO (output only) channel 5
0716CAP - channel 4 - GPO (output only) channel 7
3544CAP - channel 5 - GPO (output only) channel 11
3746CAP - channel 6 - GPO (output only) channel 13
3948CAP - channel 7 - GPO (output only) channel 15
4150CAP - channel 8 - GPO (output only) channel 17
1852 QAE - A channel 1 - GPI (input only) channel 8
19 53 QAE - B channel 1 - GPI (input only) channel 9
2054QAE - C channel 1 - GPI (input only) channel 10
25 34GPO (output only) channel 10 - Interrupt input

Test wiring according to the IO334-21 pin mapping.

Once the model has been downloaded and the target application has started, double-click the scope to see the following traces:

  • "Scope 1" shows the sine wave signals which are looped back from the analog outputs to the analog inputs

  • "Scope 2" shows the duty cycle detected by the CAP modules. The signals are generated at the digital outputs and looped back to the PWM Capture

  • "Scope 3" shows the QAE position in the first plot. The second plot shows the signals A, B and C of the quadrature encoder channel 1. The signals are looped back and captured by the digital inputs. The third plot shows the counter of generated interrupts. The interrupts are triggered by the digital output channel 10.