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Speedgoat IO33x-01LV Example

Speedgoat IO33x-01LV Example — Example showcasing the front interface

Model Name

The model is called IO33x_01LV_hdlc.slx.

Supported Modules

  • IO332-200k

  • IO333-325k, IO333-410k

Required Toolboxes

The list of basic software requirements are provided in the prerequisites section of the Getting Started page.


The IO33x-01LV example uses the following interfaces:

User Blocks

The example does not utilize any user blocks.


To test the HDL interface functionality, dedicated examples are included in the downloaded archive file. To open the examples, navigate to the corresponding folder. Note that the examples only test I/O channels for which the loopback test method is possible. The terminal board provided must be wired as described. Examples do not test I/O channels that require external hardware (for some examples a function generator or an oscilloscope is required), but running this example will still provide sufficient confirmation of the correct setup of this implementation. The examples only test interface channels which are provided by the base functionality of the I/O module. Please note that the examples provided have been color coded. The green colored subsystem (FPGA domain) is the part of the model which is actually compiled using HDL Coder and ultimately runs on the FPGA. The FPGA domain usually has a sample frequency in the range of 100 MHz and is set in the HDL Workflow Advisor (FPGA Synthesis Software Settings). The blue blocks (CPU domain) which surround the green subsystem are interfaces to the processor section of the model. The CPU domain usually has a sample frequency in the range of 1 kHz. The interrupt subsystem has been given another color (magenta), as its functionality is asynchronous to both the processor and FPGA. The interrupt source can be selected in the generated model in the Interrupt Setup block once the model has been run through the HDL Coder Workflow Advisor.

Open the example model by navigating to the folder containing the "*.slx" model file and double clicking the file. If the example is provided as a Simulink Project, navigate to the corresponding example folder and extract the Simulink project zip file. Then double-click the "*.prj" icon to open the project. After opening the project, open the model by double clicking the "*.slx" file. The model is shown as follows:

Test Wiring

Use the following test wiring to ensure the correct functionality of the example provided.

From PinTo PinTested Functionality
03 37 LVTTL_Do_1 - LVTTL_Di_1
04 38 LVTTL_Do_2 - LVTTL_Di_2
05 39 LVTTL_Do_3 - LVTTL_Di_3
06 40 LVTTL_Do_4 - LVTTL_Di_4
07 41 LVTTL_Do_5 - LVTTL_Di_5
08 42 LVTTL_Do_6 - LVTTL_Di_6
09 43 LVTTL_Do_7 - LVTTL_Di_7
10 44 LVTTL_Do_8 - LVTTL_Di_8
11 45 LVTTL_Do_9 - LVTTL_Di_9
12 46 LVTTL_Do_10 - LVTTL_Di_10
13 47 LVTTL_Do_11 - LVTTL_Di_11
14 48 LVTTL_Do_12 - LVTTL_Di_12
15 49 LVTTL_Do_13 - LVTTL_Di_13
16 50 LVTTL_Do_14 - LVTTL_Di_14
17 51 LVTTL_Do_15 - LVTTL_Di_15
18 52 LVTTL_Do_16 - LVTTL_Di_16
19 53 LVTTL_Do_17 - LVTTL_Di_17
20 54 LVTTL_Do_18 - LVTTL_Di_18
21 55 LVTTL_Do_19 - LVTTL_Di_19
22 56 LVTTL_Do_20 - LVTTL_Di_20
23 57 LVTTL_Do_21 - LVTTL_Di_21
24 58 LVTTL_Do_22 - LVTTL_Di_22
25 59 LVTTL_Do_23 - LVTTL_Di_23
26 60 LVTTL_Do_24 - LVTTL_Di_24
27 61 LVTTL_Do_25 - LVTTL_Di_25
28 62 LVTTL_Do_26 - LVTTL_Di_26
29 63 LVTTL_Do_27 - LVTTL_Di_27
30 64 LVTTL_Do_28 - LVTTL_Di_28
31 65 LVTTL_Do_29 - LVTTL_Di_29
32 66 LVTTL_Do_30 - LVTTL_Di_30
33 67 LVTTL_Do_31 - LVTTL_Di_31
34 68 LVTTL_Do_32 - LVTTL_Di_32

Running HDL Workflow Advisor

Before the example can be deployed and run on the real-time target machine, you will need to run through the HDL Coder Workflow Advisor steps to actually generate HDL code and a FPGA bitstream using HDL Coder (FPGA Synthesis Software Settings).

New: Reference design parameters, set at step 1.2 now control which interfaces will be available to target in step 1.3 of the workflow. This has reduced the total number of reference designs, and the list of interfaces available. Please remember to select the front plug-in and rear plug-in setting that is appropriate for your module, as well as the Aurora settings that should be used for your model (if applicable). These additional reference design parameter settings are further described in the interface sections for which they are relevant.

New: Prior to running the workflow advisor, be sure to double click the Select Module block in the demo model. If one or more of your modules support the model (due to available interface compatibility), a pop-up will display prompting you to select the module you would like to target. If only a single module is installed, and providing it is compatible, it will be automatically selected when the box is double clicked.

Upon completion, a newly generated model containing the Simulink Real-Time interface subsystem appears. At first sight, this subsystem resembles the FPGA subsystem. However, inside, the Simulink algorithm has been removed and replaced with blocks that the real-time application will use to communicate with the FPGA during simulation execution. The newly generated model is now ready to be deployed to a real-time target machine. To download the FPGA bitstream and the Simulink model to the target, click the Build Model button on the Simulink Editor toolbar. The real-time application loads on the Speedgoat target machine and the FPGA algorithm bitstream loads on the FPGA. If you are using I/O lines, check that you have connected the lines to the external hardware under test. Please note that some example models do have Global Delay Balancing intentionally disabled. If an error is displayed about delay balancing in step 2.3 of the HDL Coder Workflow Advisor, it can be safely ignored by checking the Ignore warnings checkbox.

Real-Time Simulation Outputs

Once the model has been downloaded and the target application has started, double-click the scope to see the following traces:

  • Display 1 and signal IO3xx_01LV_CounterRx1 show the reference 8-bit counter, the transmitted counter value and the looped-back value utilizing lines 0 to 7 and 32 to 39, which are accessed through PCIe

  • Display 2 and signal IO3xx_01LV_CounterRx2 show the reference 8-bit counter, the transmitted counter value and the looped-back value utilizing lines 8 to 15 and 40 to 47, which are accessed through PCIe

  • Display 3 and signal IO3xx_01LV_CounterRx3 show the reference 8-bit counter, the transmitted counter value and the looped-back value utilizing lines 16 to 23 and 48 to 55, which are accessed through PCIe

  • Display 4 and signal IO3xx_01LV_CounterRx4 show the reference 8-bit counter, the transmitted counter value and the looped-back value utilizing lines 24 to 31 and 56 to 63, which are accessed through PCIe

  • Display 5 and signal IO3xx_01LV_CounterDiff show the difference between the reference counter value and the looped-back counter value accessed through PCIe.