Skip to main content

Customer Login

This content is for Speedgoat customer only. Log in to see content.

Forgot your password?

Don't have a Speedgoat account? Create an account.


Speedgoat IO397 analog input, analog output and TTL example

Speedgoat IO397 analog input, analog output and TTL example — Example showcasing the front analog input, analog output and TTL interfaces.

Model Name

The model is called IO397_ad_da_dio_hdlc.slx.

Supported Modules

  • IO397-50k

Required Toolboxes

The list of basic software requirements are provided in the prerequisites section of the Getting Started page.


The IO397 analog input, analog output and TTL example uses the following interfaces:

User Blocks

The example does not utilize any user blocks.


To test the HDL interface functionality, dedicated examples are included in the downloaded archive file. To open the examples, navigate to the corresponding folder. Note that the examples only test I/O channels for which the loopback test method is possible. The terminal board provided must be wired as described. Examples do not test I/O channels that require external hardware (for some examples a function generator or an oscilloscope is required), but running this example will still provide sufficient confirmation of the correct setup of this implementation. The examples only test interface channels which are provided by the base functionality of the I/O module. Please note that the examples provided have been color coded. The green colored subsystem (FPGA domain) is the part of the model which is actually compiled using HDL Coder and ultimately runs on the FPGA. The FPGA domain usually has a sample frequency in the range of 100 MHz and is set in the HDL Workflow Advisor (FPGA Synthesis Software Settings). The blue blocks (CPU domain) which surround the green subsystem are interfaces to the processor section of the model. The CPU domain usually has a sample frequency in the range of 1 kHz. The interrupt subsystem has been given another color (magenta), as its functionality is asynchronous to both the processor and FPGA. The interrupt source can be selected in the generated model in the Interrupt Setup block once the model has been run through the HDL Coder Workflow Advisor.

The example model included shows the use of both the digital I/O channels and the ADC and DAC channels included on the front plug-in of the IO397 I/O module. Once opened, the model will appear as shown immediately below. Inside the model, shown in the second image below, functionality has been added to demonstrate the use of the digital I/O interface as well as the ADC and DAC interfaces. The model also demonstrates using the control channels to modify the sample rates of the ADC, as well as using the side channel signals to confirm the sample rates. The model reads back a running count of the ready and valid signals for the DAC and ADC respectively, as well as a free-running counter from the FPGA. The ratio of these count values is equal to the ratio of the FPGA clock to the sample rates. The constant sample rates of the ADC and DAC are confirmed on this basis. In the case of the ADC, the rate is actively throttled using a counter in the FPGA to enable the ready signal at regular intervals. A similar strategy could also be used for the DAC if necessary. The second part of the model, the digital I/O interfaces, is also demonstrated. A PCIe write is routed out, along with another PCIe enable signal, onto digital I/O line number 1. A 14-bit HDL counter is instantiated which free runs, and the highest order bit of the counter is routed to digital I/O line number 3. The highest order bit of the 14-bit counter and the PCIe-generated wave are read back into the FPGA over an external loop-back and read out with PCIe.

Open the example model by navigating to the folder containing the "*.slx" model file and double clicking the file. If the example is provided as a Simulink Project, navigate to the corresponding example folder and extract the Simulink project zip file. Then double-click the "*.prj" icon to open the project. After opening the project, open the model by double clicking the "*.slx" file. The model is shown as follows:

Test Wiring

Use the following test wiring to ensure the correct functionality of the test model provided.

From PinTo PinTested Functionality
1A9AAnalog input channel 01+ to analog output channel 01
2A13AAnalog input channel 01- to GND
3A10AAnalog input channel 02+ to analog output channel 02
4A13AAnalog input channel 02- to GND
5A11AAnalog input channel 03+ to analog output channel 03
6A13AAnalog input channel 03- to GND
7A12AAnalog input channel 04+ to analog output channel 04
8A13AAnalog input channel 04- to GND
3b9BDIO 0 to DIO 6
5b11BDIO 2 to DIO 8
13b11B7BDIO 10 to DIO 12 to DIO 4

Running HDL Workflow Advisor

Before the example can be deployed and run on the real-time target machine, you will need to run through the HDL Coder Workflow Advisor steps to actually generate HDL code and a FPGA bitstream using HDL Coder (FPGA Synthesis Software Settings).

New: Reference design parameters, set at step 1.2 now control which interfaces will be available to target in step 1.3 of the workflow. This has reduced the total number of reference designs, and the list of interfaces available. Please remember to select the front plug-in and rear plug-in setting that is appropriate for your module, as well as the Aurora settings that should be used for your model (if applicable). These additional reference design parameter settings are further described in the interface sections for which they are relevant.

New: Prior to running the workflow advisor, be sure to double click the Select Module block in the demo model. If one or more of your modules support the model (due to available interface compatibility), a pop-up will display prompting you to select the module you would like to target. If only a single module is installed, and providing it is compatible, it will be automatically selected when the box is double clicked.

Upon completion, a newly generated model containing the Simulink Real-Time interface subsystem appears. At first sight, this subsystem resembles the FPGA subsystem. However, inside, the Simulink algorithm has been removed and replaced with blocks that the real-time application will use to communicate with the FPGA during simulation execution. The newly generated model is now ready to be deployed to a real-time target machine. To download the FPGA bitstream and the Simulink model to the target, click the Build Model button on the Simulink Editor toolbar. The real-time application loads on the Speedgoat target machine and the FPGA algorithm bitstream loads on the FPGA. If you are using I/O lines, check that you have connected the lines to the external hardware under test. Please note that some example models do have Global Delay Balancing intentionally disabled. If an error is displayed about delay balancing in step 2.3 of the HDL Coder Workflow Advisor, it can be safely ignored by checking the Ignore warnings checkbox.

Real-Time Simulation Outputs

Once the model has been downloaded, a look-up table in the CPU domain feeds the DAC channels new data values over PCIe writes. The DAC channels are then read back over the ADC channels via the loop-back wiring. These read-in values are then written over PCIe outputs so that they can be observed with a target scope:

  • Display 1 IO397_AI_CH1_2 shows the read-back signal from the analog inputs. Two sine waves on this scope confirm that the loop-back has worked correctly

  • Display 2 IO397_SampleFrequencies_ADC_DAC shows the sample rates of the analog inputs and analog outputs

  • Display 3 IO397_DI_CH6_8 shows the read-back signal from the digital I/O lines. A pair of slightly phase-shifted square waves confirms that PCIe-to-digital I/O, as well as internally generated digital I/O signals, are being correctly generated and acquired over the digital I/O lines

  • Display 4 IO397_DI_CH4 shows the Bi-Directional signals

    • IO397_DI_CH4:1 shows the output enable for the output signal DO10 (high) and DO12 (low)

    • IO397_DI_CH4:2 shows the state of the digital I/O channel 4.