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Documentation
CONTENTS

Speedgoat IO342-63 Interface

Speedgoat IO342-63 Interface — Front interfaces with four analog input and four analog output lines

Supported Modules

  • IO342-1450k, IO342-1080k

Reference Design Parameter

The -63 interface is implemented as a front plugin of the IO342. Please be sure to select -63 (or -63-63 if dual FMC cards are mounted) from the front plugin pulldown menu at step 1.2 to make the interface available in step 1.3 of the workflow advisor.

Interface Components

IO342-63 AI Data [0:3]

IO342-63 AI Data [0:7]

  • 4 or 8 channels

  • Data Type: int16 x 8 at a rate of 125 MHz.

  • Direction: input

  • Data Ordering: The 8 16-bit values are the sequential samples from the analog input. Since the analog input runs at 1 GSPS, it is required to read multiple samples simultaneously. Data{1} is sample n, and Data{8} is sample n+7.

  • Input voltage range:

    • DC Coupled: (50 Ω)

    • DC to 400 MHz: +4 dBm / 1.0 Vp-p DC (Max )

    • DC to 1000 MHz: -5.0 dBm (Max)

    Note: The maximum supported amplitude reduces with increasing frequency above 400 MHz. See ADS54J60 Manual on “Maximum Supported Input Amplitude”.

IO342-63 AI Valid [0:3]

IO342-63 AI Valid [0:7]

This mandatory port indicates when the analog input data is valid. The port signal is a single clock pulse of the design under test (DUT) frequency. Since the DUT can be set to run faster than the ADC, there will not necessarily be valid data available at every clock tick.

  • The AI Valid for the corresponding AI Data is mandatory

  • Data Type: boolean

  • Direction: input

Note: Due to the sample clock to design under test (DUT) clock crossing, valid is not held constantly high, but periodically goes low for one clock tick.

IO342-63 AO Data [0:3]

IO342-63 AO Data [0:7]

  • 4 or 8 channels

  • Data Type: int16 x 8 at a rate of 125 MHz.

  • Direction: output

  • Data Ordering: The 8 16-bit values are the sequential samples for the analog output. Since the analog output runs at 1 GSPS, it is required to read multiple samples simultaneously. Data{1} is sample n, and Data{8} is sample n+7.

  • Output voltage range:

    • DC Coupled: (50 Ω)

    • DC to 400 MHz: +4 dBm / 1.0 Vp-p DC (Max )

    • DC to 1000 MHz: -5.0 dBm (Max)

    Note: The maximum supported amplitude reduces with increasing frequency above 400 MHz. See ADS54J60 Manual on “Maximum Supported Input Amplitude”.

IO342-63 AO Trigger [0:3]

IO342-63 AO Trigger [0:7]

This mandatory port triggers the analog outputs. Ideally the trigger signal should be implemented as a single clock pulse of the design under test (DUT) frequency.

  • The AO Trigger for the corresponding AO Datais mandatory

  • Data Type: boolean

  • Direction: output

IO342-63 AO Ready [0:3]

IO342-63 AO Ready [0:7]

This non-mandatory port indicates to the design under test (DUT) that the analog output conversion has completed. When the conversion completes, this signal will go high, to indicate to the DUT that a new data value can be passed to the analog output.

  • The AO Ready for the corresponding AO Data is non-mandatory

  • Data Type: boolean

  • Direction: input

Notes: When the ready signal goes low, the trigger should react within one clock cycle by going low. When ready goes high, the trigger should also react within a single clock so that the small clock crossing data buffer is not exhausted. Ready goes low when two values are in the FIFO buffer, and goes high when this drops down to 1. Please also note that due to the clock crossing, Ready is not held constantly high, but periodically goes low for one clock. The ratio of time spent ready to time spent not ready is related to the ratio of the analog output clock (125 MHz) to the DUT clock (strictly > 125 MHz). Use ready to control the flow of your data into the analog output, and withdraw trigger to hold the current value.

Interface Pin Mapping

The pin mapping for the IO342-63 primary FMC slot is as follows:

Coax SMC ConnectorData TypeTarget Platform InterfacesBit Range Address FPGA Pin
A0

int16 x 8

IO342-63 AI Data

Channel 01

D0

int16 x 8

IO342-63 AO Data

Channel 01

D1

int16 x 8

IO342-63 AO Data

Channel 02

A1

int16 x 8

IO342-63 AI Data

Channel 02

CLCLOCK IN
TRTRIGGER IN
A2

int16 x 8

IO342-63 AI Data

Channel 03

D2

int16 x 8

IO342-63 AO Data

Channel 03

D3

int16 x 8

IO342-63 AO Data

Channel 04

A3

int16 x 8

IO342-63 AI Data

Channel 04

The pin mapping for the IO342-63 secondary FMC slot is as follows:

Coax SMC ConnectorData TypeTarget Platform InterfacesBit Range Address FPGA Pin
D0

int16 x 8

IO342-63 AO Data

Channel 05

A0

int16 x 8

IO342-63 AI Data

Channel 05

D1

int16 x 8

IO342-63 AO Data

Channel 06

A1

int16 x 8

IO342-63 AI Data

Channel 06

CLCLOCK IN
TRTRIGGER IN
A2

int16 x 8

IO342-63 AI Data

Channel 07

D2

int16 x 8

IO342-63 AO Data

Channel 07

D3

int16 x 8

IO342-63 AO Data

Channel 08

A3

int16 x 8

IO342-63 AI Data

Channel 08

Note: The Trigger inputs are not active, but the CLOCK IN ports can be used to supply a 10 MHz or 100 MHz reference clock as an alternative to the internal clock source, which will be used for generating the sample clock. The setting for the input reference clock source will be promoted to the mask of your generated model. Select your desired reference clock source. The default is the internal clock generator.

Terminal Board

This interface does not require a terminal board.