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CONTENTS

Speedgoat IO3xx-22 Interface

Speedgoat IO3xx-22 Interface — Rear interface with 16 RS422/RS485, 24 TLL and 6 I2C compatible (bi-directional) I/O lines

Supported Modules

  • IO332-200k

  • IO333-325k, IO333-410k, IO333-325k-SFP, IO333-410k-SFP

  • IO334-325k, IO335-325k

  • IO342-1080k, IO342-1450k (only 4 RS485/RS422, 6 TTL and 2 I2C compatible (bi-directional) I/O lines)

Reference Design Parameters

Select "-22" as your reference design's rear plug-in using the pull-down menu in step 1.2 of the workflow advisor so that the appropriate interfaces will be available in step 1.3 of the workflow.

Bidirectional Interface Description

Bidirectional signals require both an input buffer and an output buffer with a switchable 3-state driver. The figure below shows the implementation of a bidirectional interface using a generic IOBUF primitive.

  • A logic high ('1') from the Bidirectional Output Enable FPGA-Logic enables the output buffer (3-state is off → I/O pin acts as an output).

    In this situation, the I/O pin will be driven to the same condition as the Bidirectional Output FPGA-Logic.

    The Bidirectional Input FPGA-Logic is the same as the Bidirectional Output FPGA-Logic due to the loopback via the input buffer.

  • A logic low ('0') on the Bidirectional Output Enable FPGA-Logic disables the output buffer (3-state is 'Hi Z' → I/O pin acts as an input).

    In this situation, the condition of the I/O pin is buffered from the input buffer and forwarded to the Bidirectional Input FPGA-Logic. The condition of the Bidirectional Output FPGA-Logic has no effect.

Bidirectional Output EnableBidirectional OutputBidirectional InputI/O Pin
0X= I/O PinZ
1111
1000

Differential Interface

The IO3xx-22 read signal conditioning module provides 16 differential I/O lines with a RS422/485 compatible transceiver.

RS422/RS485 IO3xx-22 [0:n]

This port is automatically connected to either I (Input) from FPGA Logic if it is an input port or to O (Output) to FPGA Logicif it is an output port. The direction T 3-state input of the corresponding interface is automatically determined by Simulink, providing the RS422/RS485 IO3xx-22 Bidirectional Output Enable signal is not assigned for the corresponding bits.

  • Data Type: boolean

  • Direction: input or output

RS422/RS485 IO3xx-22 Output Enable [0:n]

The inverted value of this port is connected to the T 3-state input port of the IOBUF primitive.

  • Data Type: boolean

  • Direction: output

  • Signal is logic '1': the bidirectional port is acting as output. Signal is logic '0': the bidirectional port is acting as input

TTL Interface

TTL IO3xx-22 Channel [0:m]

The IO3xx-22 rear signal conditioning module provides 24 TTL I/O lines. The I/O lines are distributed in 3 groups of 8 lines. All 8 lines of a group must have the same direction and pull resistor configuration. Once the model is generated using HDL Workflow Advisor, the pull resistors of the 3 I/O port groups can be configured using the mask of the generated algorithm block.

  • Supported pull-resistors: pull-up 3.3 V, pull-up 5 V, pull-down, floating

  • Data Type: boolean

  • Direction: input or output

Bidirectional Interface

The IO3xx-22 rear signal conditioning module provides 6 I2C compatible (bi-directional) TTL I/O lines

TTL IO3xx-22 Bidirectional Output Enable [0:N]

The inverted value of this port is connected to the T 3-state input port of the IOBUF primitive.

  • Data Type: boolean

  • Direction: output

  • Signal is logic '1': the bidirectional port is acting as output. Signal is logic '0': the bidirectional port is acting as input

TTL IO3xx-22 Bidirectional Output [0:N]

This port is connected to the I (Input) from FPGA Logic port of the IOBUF primitive.

  • Data Type: boolean

  • Direction: output

TTL IO3xx-22 Bidirectional Input Channel [0:N]

This port is connected to the O (Output) to FPGA Logic port of the IOBUF primitive.

  • Data Type: boolean

  • Direction: input

Interface Pin Mapping

The pin mapping for the IO3xx-22 rear plug-in is as follows:

Terminal PinData TypeTarget Platform InterfacesBit Range Address FPGA PinPort
IO33xIO342
1booleanRS422/RS485 IO3xx-22 [0:n]0 (+)0 (+) 
2booleanRS422/RS485 IO3xx-22 [0:n]1 (+)  
3booleanRS422/RS485 IO3xx-22 [0:n]2 (+)  
4booleanRS422/RS485 IO3xx-22 [0:n]3 (+)  
5booleanRS422/RS485 IO3xx-22 [0:n]4 (+)  
6booleanRS422/RS485 IO3xx-22 [0:n]5 (+)  
7booleanRS422/RS485 IO3xx-22 [0:n]6 (+)1 (+) 
8booleanRS422/RS485 IO3xx-22 [0:n]7 (+)  
9Ground
10booleanRS422/RS485 IO3xx-22 [0:n]8 (+)2 (+) 
11booleanRS422/RS485 IO3xx-22 [0:n]9 (+)  
12booleanRS422/RS485 IO3xx-22 [0:n]10 (+)  
13booleanRS422/RS485 IO3xx-22 [0:n]11 (+)  
14booleanRS422/RS485 IO3xx-22 [0:n]12 (+)  
15booleanRS422/RS485 IO3xx-22 [0:n]13 (+)3 (+) 
16booleanRS422/RS485 IO3xx-22 [0:n]14 (+)  
17booleanRS422/RS485 IO3xx-22 [0:n]15 (+)  
18booleanTTL IO3xx-22 [0:m]001
19booleanTTL IO3xx-22 [0:m]111
20booleanTTL IO3xx-22 [0:m]2 1
21booleanTTL IO3xx-22 [0:m]3 1
22booleanTTL IO3xx-22 [0:m]4 1
23booleanTTL IO3xx-22 [0:m]5 1
24booleanTTL IO3xx-22 [0:m]6 1
25booleanTTL IO3xx-22 [0:m]7 1
26Ground
27booleanTTL IO3xx-22 [0:m]822
28booleanTTL IO3xx-22 [0:m]932
29booleanTTL IO3xx-22 [0:m]10 2
30booleanTTL IO3xx-22 [0:m]11 2
31booleanTTL IO3xx-22 [0:m]12 2
32booleanTTL IO3xx-22 [0:m]13 2
33booleanTTL IO3xx-22 [0:m]14 2
34booleanTTL IO3xx-22 [0:m]15 2
35booleanRS422/RS485 IO3xx-22 [0:n]0 (-)0 (-) 
36booleanRS422/RS485 IO3xx-22 [0:n]1 (-)  
37booleanRS422/RS485 IO3xx-22 [0:n]2 (-)  
38booleanRS422/RS485 IO3xx-22 [0:n]3 (-)  
39booleanRS422/RS485 IO3xx-22 [0:n]4 (-)  
40booleanRS422/RS485 IO3xx-22 [0:n]5 (-)  
41booleanRS422/RS485 IO3xx-22 [0:n]6 (-)1 (-) 
42booleanRS422/RS485 IO3xx-22 [0:n]7 (-)  
43Ground
44booleanRS422/RS485 IO3xx-22 [0:n]8 (-)2 (-) 
45booleanRS422/RS485 IO3xx-22 [0:n]9 (-)  
46booleanRS422/RS485 IO3xx-22 [0:n]10 (-)  
47booleanRS422/RS485 IO3xx-22 [0:n]11 (-)  
48booleanRS422/RS485 IO3xx-22 [0:n]12 (-)  
49booleanRS422/RS485 IO3xx-22 [0:n]13 (-)3 (-) 
50booleanRS422/RS485 IO3xx-22 [0:n]14 (-)  
51booleanRS422/RS485 IO3xx-22 [0:n]15 (-)  
52booleanTTL IO3xx-22 [0:m]16 3
53booleanTTL IO3xx-22 [0:m]17 3
54booleanTTL IO3xx-22 [0:m]1843
55booleanTTL IO3xx-22 [0:m]1953
56booleanTTL IO3xx-22 [0:m]20 3
57booleanTTL IO3xx-22 [0:m]21 3
58booleanTTL IO3xx-22 [0:m]22 3
59booleanTTL IO3xx-22 [0:m]23 3
60Ground
61boolean

IO3xx-22 Bidirectional Direction Channel [0:N]

IO3xx-22 Bidirectional Output Channel [0:N]

IO3xx-22 Bidirectional Input Channel [0:N]

0  
62boolean

IO3xx-22 Bidirectional Direction Channel [0:N]

IO3xx-22 Bidirectional Output Channel [0:N]

IO3xx-22 Bidirectional Input Channel [0:N]

1  
63boolean

IO3xx-22 Bidirectional Direction Channel [0:N]

IO3xx-22 Bidirectional Output Channel [0:N]

IO3xx-22 Bidirectional Input Channel [0:N]

20 
64boolean

IO3xx-22 Bidirectional Direction Channel [0:N]

IO3xx-22 Bidirectional Output Channel [0:N]

IO3xx-22 Bidirectional Input Channel [0:N]

31 
65boolean

IO3xx-22 Bidirectional Direction Channel [0:N]

IO3xx-22 Bidirectional Output Channel [0:N]

IO3xx-22 Bidirectional Input Channel [0:N]

4  
66boolean

IO3xx-22 Bidirectional Direction Channel [0:N]

IO3xx-22 Bidirectional Output Channel [0:N]

IO3xx-22 Bidirectional Input Channel [0:N]

5  
67+5 V / 24 mA supply
68+5 V / 24 mA supply

The Interface MSB depends on the I/O Module:

 IO33xIO342
m153
n235
N51

Terminal Board

The pin mapping goes with the following terminal board: