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SSI Protocol

Code Module for SSI Communication Protocol 


SSI (Synchronous Serial Interface) is a synchronous, point-to- point, serial communication channel for digital data transmission. A common clock signal is used on the receiving and sending side. 
SSI has a high protocol efficiency and can be implemented over various hardware platforms, making it very popular among sensor manufacturers. 
This code module is designed for different packet transmission frequencies and is also available in both I/O module families: configurable I/O modules used to configure I/O and protocol functionalities for a given code module delivered as part of a Custom Implementation Package; and Simulink®-programmable FPGA I/O modules optimized for use with the MathWorks® HDL Coder™ toolbox. 

Three Code Modules are available:

  • SSI Master
  • SSI Slave
  • SSI Sniffer

Common Applications

  • Interface to standalone absolute encoders
  • Ideal for applications that must be reliable and robust, for example in industrial environments
  • Motor control for feedback loop
  • Industrial machinery position control
  • Various control applications with absolute position feedback
SSI Configuration  
Data size

1 bit to 32 bits

Clocking frequency 100 kHz to 2 MHz
Coding Binary or gray
SSI2 Supported
SSI Master FPGA Code Module 
Purpose Receives SSI protocol messages
  • Configurable data size  
  • Configurable frequency 
  • Configurable time pause 
  • Configurable time low 
  • Configurable decoding: gray or binary 
  • SSI1 and SSI2 supported 
SSI Slave FPGA Code Module 
Purpose Transmits SSI protocol messages, emulates SSI encoder 
  • Configurable data size  
  • Configurable frequency 
  • Configurable transfer timeout 
  • Configurable clock timeout 
  • Configurable coding: gray or binary 
  • SSI1 and SSI2 support 
SSI Sniffer FPGA Code Module 
 Purpose Monitors existing SSI communications between master and slave
  • Determines the clock frequency 
  • Determines the data size (number of bits) 
  • Determines if the data is binary coded or gray 
  • Determines number of bits error  
  • Configurable decoding: gray or binary 
Item ID Product Name Components
303MOT Motion Control HDL I/O Blockset
  • Simulink® blocks and the corresponding VHDL files to use code module functionality in the HDL Coder™ workflow  
  • Simulink® example model 
  • Simulink® library for configuration and utility blocks 
  • Comprehensive documentation  
203XXA  Configuration File
  • IO functionality (configuration file) according to customer requirements
  • Simulink® example model 
  • Simulink® library  
  • Comprehensive documentation   

Pricing information
We don't publish pricing information on our website. Upon request by e-mail or phone we can provide a complete price list covering our entire product portfolio in various currencies. We recommend that you get in touch with us to discuss your specific needs. We can then quickly provide you with a tailored quotation including technical and pricing information.

Included in the Delivery

For our configurable FPGA I/O modules, offered as part of a Custom Implementation Package: 

  • IO functionality (configuration file) according to customer requirements
  • Simulink® example models 
  • Simulink® library 
  • Comprehensive documentation 

For our Simulink®-programmable FPGA I/O modules, offered as part of the Motion Control HDL I/O Blockset: 

  • Simulink® blocks and the corresponding VHDL files to use code module functionality in the HDL Coder™ workflow 
  • Simulink® library, a sample Simulink model and comprehensive documentation 

Supported I/O modules

  • All configurable and Simulink®-programmable FPGA I/O modules featuring digital I/O lines (primarily TTL) 
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