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Code Module for Dshot Communication Protocol 


Dshot (Digital shot) is a digital protocol for Flight-Controller(FC)-to-Electronic-Speed-Controller(ESC) communication used in unmanned aerial vehicle (UAV) applications.

Dshot digital protocols are resistant to electrical noise and jitter as each pulse represents one binary digit (bit). The bit 0 and bit 1 signals are distinguished by their high times.  
Dshot offers a checksum for cyclic redundancy checking with high-resolution data and does not require ESC calibration. This code module is designed for different packet transmission frequencies and is also available in both FPGA I/O module families: configurable FPGA I/O modules used to configure I/O and protocol functionalities for a given FPGA code module delivered as part of a Custom Implementation Package; and Simulink-programmable FPGA I/O modules optimized for use with the MathWorks HDL Coder™ toolbox. 

Common Applications

  • Hardware-in-the-loop simulation of a FC such as Pixhawk 
  • Rapid control prototyping for the development of high-performance ESC to save power, increase agility and improve reliability
Dshot Mode Dshot 150  Dshot 300 Dshot 600 Dshot 1200
Data packet (16 bit) 
  • 11-bit throttle value* 
  • 4-bit CRC checksum 
  • 1-bit telemetry request 
Bit rate  150 kb/s 300 kb/s 600 kb/s  1200 kb/s
Frequency  9.37 kHz 18.7 kHz 37.5 kHz   75 kHz 
Latency  106.72 µs  53.44 µs  26.7 µs  13.3 µs 
Possible FC loop frequency  8.33 kHz (2-bit reset)  16.6 kHz (2-bit reset)  33 kHz (2-bit reset)  66 kHz (2-bit reset) 
Recommended FC loop frequency  4.05 kHz (21-bit reset time)  8.09 kHz (21-bit reset time)  16 kHz (21-bit reset time)  32 kHz (21-bit reset time) 

*2,000-step throttle value. Values 1-47 are reserved for the telemetry settings. 0 is reserved for disarming. 

Dshot RX FPGA Code Module 
Purpose Receives Dshot protocol messages 
  • Dshot mode selection (Dshot 150, Dshot 300, Dshot 600, Dshot 1200) 
  • Configurable reset time 
  • Checksum verification 
  • Telemetry data indication 
Dshot Tx FPGA Code Module 
Purpose Transmits Dshot protocol messages 
Capabilities  Dshot mode selection (Dshot 150, Dshot 300, Dshot 600, Dshot 1200) 
Timing Information 
 Pulse sequence  time-2
Protocol Type  Dshot 150  Dshot 300 Dshot 600 Dshot 1200
Period time  6.67 µs  3.33 µs  1.67 µs  0.833 µs 
Zero high time (T0H)  2.50 µs  1.25 µs  0.625 µs  0.313 µs 
One high time (T1H)  5.00 µs  2.50 µs  1.25 µs  0.625 µs 
Item ID Product Name Components
303COM  Communication HDL I/O Blockset
  • Simulink blocks and the corresponding VHDL files to use code module functionality in the HDL Coder workflow  
  • Simulink example model 
  • Simulink library for configuration and utility blocks 
  • Comprehensive documentation  
203XXA  Custom Implementation Package 
  • Project-specific FPGA bitstream implemented with the required number of code module channels 
  • Simulink example model 
  • Simulink library  
  • Comprehensive documentation   

Pricing information
We don't publish pricing information on our website. Upon request by e-mail or phone we can provide a complete price list covering our entire product portfolio in various currencies. We recommend that you get in touch with us to discuss your specific needs. We can then quickly provide you with a tailored quotation including technical and pricing information.


Included in the Delivery

For our configurable FPGA I/O modules, offered as part of a Custom Implementation Package: 

  • FPGA bitstream implemented according to customer requirements 
  • Simulink® example models 
  • Simulink library 
  • Comprehensive documentation 

For our Simulink-programmable FPGA I/O modules, offered as part of the Communication HDL I/O Blockset: 

  • Simulink blocks and the corresponding VHDL files to use code module functionality in the HDL Coder workflow 
  • Simulink library, a sample Simulink model and comprehensive documentation 

Supported I/O modules

  • All configurable and Simulink-programmable FPGA I/O modules featuring digital I/O lines (primarily TTL) 
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