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FPGA Code Modules

Many applications require high frequency connectivity and industry-specific communication protocols to interact with their Simulink models. Examples include motor control, hardware-in-the-loop (HIL) simulation, encoder emulation and multi-gigabyte high-speed communications. Speedgoat FPGA code modules (IP Cores) provide additional I/O connectivity and communication protocols support, easily configurable using the included Simulink blocks, for high frequency digital signal generation and capture.

FPGA code modules are compatible with both programmable FPGAs and configurable FPGAs. That is, they can be used both within Simulink Real-Time workflow or the HDL Coder workflow.

FPGA Code Modules

Distribution

The FPGA code module functionality is distributed either as a Custom Implementation (CI), or as a Netlist.

MathWorks Workflow Use case Name of distribution package Contents of delivery
HDL Coder workflow Application created from Simulink runs on programmable FPGAs Netlist
  • Simulink block with integrated Netlist, providing functionality for a specific FPGA Code Module
  • Simulink test model
  • Comprehensive documentation
  • I/O pin mappings can be defined on your own as needed using HDL Coder workflow advisor, and the Simulink block
Simulink Real-Time workflow Application created from Simulink runs on CPU of target machine Custom implementation (CI) for IO3XX I/O module
  • Speedgoat FPGA configuration file, implementing your required predefined types and channel counts of the various FPGA code modules (selectable in setup block of IO3XX FPGA I/O module)
  • Simulink driver blocks for FPGA Code Modules
  • Simulink test model
  • Comprehensive documentation including I/O pin mapping information

Note: Programmable FPGAs can follow the same workflow as configurable FPGAs. That is, they can use FPGA code modules as Custom Implementations as well.

Essentially, a Speedgoat FPGA I/O module with custom implementation works like any other I/O module, but the FPGA enables sampling of high frequency signals at much faster rates than the fundamental closed-loop sample rate, and enables reconfiguration of provided functionality at any time.

Netlists are typically combined with your own Simulink design, from which VHDL code is automatically created using HDL Coder. See our introduction How to build, run, and test real-time applications with HDL Coder

Overview of FPGA Code Modules

General Purpose

Type
DIO - General Purpose Digital I/O
INT - Interrupt code module
Synchronisation code module

Protocols

Type Master Slave Sniffer
SPI
I2C On request
Aurora 64B/66B  
RS485 / RS422  (UART)  

PWM Generation and Capture

Type Generation Capture  
PWM  

Encoder Measurement and Simulation

Type Decoder (Measurement) Encoder (Simulation) Sniffer
Quadrature  
SSI (Absolute)  
SSI2  
BiSS
EnDAT 2.2
Cam and Crank  

Support for additional functionality is available on request - please contact us

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