Distribution
The FPGA code module functionality is distributed either as a Custom Implementation (CI), or as a Netlist.
| MathWorks Workflow |
Use case |
Name of distribution package |
Contents of delivery |
| HDL Coder workflow |
Application created from Simulink runs on Simulink-programmable FPGAs |
Netlist |
- Simulink block with integrated Netlist, providing functionality for a specific FPGA Code Module
- Simulink test model
- Comprehensive documentation
- I/O pin mappings can be defined on your own as needed using HDL Coder workflow advisor, and the Simulink block
|
| Simulink Real-Time workflow |
Application created from Simulink runs on CPU of target machine |
Custom implementation (CI) for IO3XX I/O module |
- Speedgoat FPGA configuration file, implementing your required predefined types and channel counts of the various FPGA code modules (selectable in setup block of IO3XX FPGA I/O module)
- Simulink driver blocks for FPGA Code Modules
- Simulink test model
- Comprehensive documentation including I/O pin mapping information
|
Note: Simulink-programmable FPGAs can follow the same workflow as configurable FPGAs. That is, they can use FPGA code modules as Custom Implementations as well.
Essentially, a Speedgoat FPGA I/O module with custom implementation works like any other I/O module, but the FPGA enables sampling of high frequency signals at much faster rates than the fundamental closed-loop sample rate, and enables reconfiguration of provided functionality at any time.
Netlists are typically combined with your own Simulink design, from which HDL code is automatically created using HDL Coder. See our introduction How to build, run, and test real-time applications with HDL Coder