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Simulink Programmable FPGA I/O search search close

High-frequency signal processing requires sub-microsecond closed-loop rates. Simulink-programmable FPGA I/O modules provide high-bandwidth and ultra-low latency.

Benefit from the following features

  • Seamless integration with MathWorks HDL Coder™  workflow for automatic HDL code generation.
  • Many MathWorks tools and toolboxes such as Simulink, Simscape™ and Simcape Electrical™support this workflow.
  • A vast range of I/O and protocol functionalities is turnkey supported using HDL I/O Blocksets.
  • Inter-module communication through multi-gigabit, high-speed protocols, such as Xilinx Aurora.
Simulink-Programmable FPGA I/O Modules

Selection Guide

To achieve very high closed-loop rates (up to multiple MHz) the FPGA I/O modules include their own local I/O in order to bypass the limitations of the relatively slow PCI bus. This local I/O is either integrated into the module or can be added as a plug-in. The Selection Guide below shows the wide range of analog, digital, and fiber optic transceivers available.

Legend

Compatible test systems: P - Performance | B - Baseline | M - Mobile | U - Unit real-time target machine
I/O Module Type: C: Configurable I/O Module | S: Simulink-Programmable FPGA
I/O module System FPGA chip Logic Cells
( x103 )
I/O interface Additional I/O interface Max. sample rate [kHz] Output range
In / Out
IO324C, S P, B, M Xilinx Artix-7 200 32 x analog In
8 x analog Out
32 x TTL
8 x RS-422/RS-485
Selectable via plug-ins:
56 TTL or 24 TTL & 32 RS422/RS485
1000 0.6V to +24.576V /
-10V to +10V
IO332C, S P, B, M Xilinx Artix-7 200 Selectable via plug-ins:
64 LVTTL or 30 RS485 or 16 CMOS & 22 RS485 or 30 LVDS or 16 A/Ds, 8 D/As & 16 TTL
Selectable via plug-ins:
56 TTL or 24 TTL & 32 RS422/RS485 and 4 MGT
model sample rate 0 to +3.3V, -6V to +6V,
0 to 5V, 0 to 4V /
0 to +3.3V, -6V to +6V,
0 to 5V, 0 to 4V
IO333C, S P, B, M Xilinx Artix-7 410 Selectable via plug-ins:
64 LVTTL or 30 RS485 or 16 CMOS & 22 RS485 or 30 LVDS or 16 A/Ds, 8 D/As & 16 TTL
Selectable via plug-ins:
56 TTL or 24 TTL & 32 RS422/RS485 and 4 MGT
model sample rate 0 to +3.3V, -6V to +6V,
0 to 5V, 0 to 4V /
0 to +3.3V, -6V to +6V,
0 to 5V, 0 to 4V
IO333-SFPS P, B, M Xilinx Artix-7 410 26 LVCMOS or 13 LVDS
2 SFP
Selectable via plug-ins:
56 TTL or 24 TTL & 32 RS422/RS485 and 4 MGT
model sample rate -
IO334S P, B, M Xilinx Kintex-7 325 16 x 16-bit analog In
16 x 16-bit analog Out
Selectable via plug-ins:
56 TTL or 24 TTL & 32 RS422/RS485 and 4 MGT
model sample rate -20V to +20V /
-10V to +10V
IO335S P, B, M Xilinx Kintex-7 325 24 x 16-bit analog In Selectable via plug-ins:
56 TTL or 24 TTL & 32 RS422/RS485 and 4 MGT
model sample rate -10V to +10V /
-
IO342S P, B, M Xilinx Kintex-7 Ultrascale 1450 Selectable via plug-ins:
2 QSFP or 4 analog I/O
Selectable via plug-ins:
56 TTL or 24 TTL & 32 RS422/RS485 and 4 MGT
model sample rate -
IO397C, S B, U Xilinx Artix-7 50 4 x analog In
4 x analog Out
14 x TTL
- 200 -10.24V to +10.24V /
-10.8V to +10.8V

Capabilities

Speedgoat FPGA I/O modules and Simulink Real-Time™, together with Simulink Coder™ for C, and HDL Coder™ for HDL code generation make it easy to leverage all the benefits of FPGA technology:

Task With Simulink Coder only With HDL Coder
Acquire and generate high-frequency analog and digital signals up to 10 Gsps
Achieve closed-loop sample rates up to 20-100kHz depending on model complexity and I/O channel count
Achieve closed-loop rates above 20-100kHz, depending on model complexity and I/O channel count  
Pre-process or replay signal data on FPGAs  
Leverage FPGA code modules with FPGA I/O modules
Run floating and fixed point implementations
(some restrictions with HDL Coder may apply depending on your application and the MATLAB release used)
Integrate custom HDL code into Simulink design  
Log data to x86 RAM, SSD, or to external RAM of the FPGA I/O module
Run algorithms designed with Simulink on multiple CPU cores and multiple synchronized target machines, at multiple synchronized sample rates  
Run algorithms designed with Simulink on multiple CPU cores and CPUs, and multiple FPGAs, interconnected with low-latency links, at multiple synchronized sample rates
Monitor parameters and tune application during real-time execution
 
 

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