Selection Guide

To achieve very high closed-loop rates (up to multiple MHz) the FPGA I/O modules include their own local I/O in order to bypass the limitations of the relatively slow PCI bus. This local I/O is either integrated into the module or can be added as a plug-in. The Selection Guide below shows the wide range of analog, digital, and fiber optic transceivers available.

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Capabilities

Speedgoat FPGA I/O modules and Simulink Real-Time™, together with Simulink Coder™ for C, and HDL Coder™ for HDL code generation make it easy to leverage all the benefits of FPGA technology:

Task	With Simulink Coder only	With HDL Coder
Acquire and generate high-frequency analog and digital signals up to 10 Gsps
Achieve closed-loop sample rates up to 20-100kHz depending on model complexity and I/O channel count
Achieve closed-loop rates above 20-100kHz, depending on model complexity and I/O channel count
Pre-process or replay signal data on FPGAs
Leverage FPGA code modules with FPGA I/O modules
Run floating and fixed point implementations (some restrictions with HDL Coder may apply depending on your application and the MATLAB release used)
Integrate custom HDL code into Simulink design
Log data to x86 RAM, SSD, or to external RAM of the FPGA I/O module
Run algorithms designed with Simulink on multiple CPU cores and multiple synchronized target machines, at multiple synchronized sample rates
Run algorithms designed with Simulink on multiple CPU cores and CPUs, and multiple FPGAs, interconnected with low-latency links, at multiple synchronized sample rates
Monitor parameters and tune application during real-time execution