This FPGA code module provides SPI master and slave support implemented on a Simulink Programmable FPGA.
The code module can function as either master or slave, and multiple slave select lines can be implemented as required. Most typical applications are directly supported. Speedgoat offers a customisation service to meet any particular requirements you may have.
SPI sniffer functionality is provided by the SPI Sniffer FPGA code module.
An example timing diagram of the signal generated / read by the SPI FPGA code module
T 1 = Start delay (master only)
T 2 = Clock divider
T 3 = Inter-word delay (master only)
T 4 = Stop delay (master only)