This FPGA code module provides interrupt support implemented on a Simulink Programmable FPGA. It allows models to be executed on high-to-low or low-to-high transition events instead of being based on the CPU timer.
Speedgoat Simulink Programmable FPGAs come with interrupt generation support for the PWM generation FPGA code module by default. The standard interrupt implementation requires one input line and requests the interrupt (#intA) as defined in the provided Simulink Real-Time driver blockset. Other interrupt generation events can be implemented on request for the PWM and other FPGA code modules, for example when a tasks completes, reaches a specific stage, or an error occurs. Please contact us with your requirements.
Supported parameter settings
defines the duration where the interrupt input signal is tested. If the signal is stable for the specifieds time, the FPGA declares it is a valid signal and asserts the interrupt. Enter '0' in this field to turn off the feature. Interrupt delay:
Optional delay before asserting the interrupt. Polarity:
the FPGA can assert the interrupt when the input signal is rising (value '0') or falling (value '1').