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Event based interrupt support for Simulink programmable FPGAs

This code module provides interrupt support implemented on a Simulink Programmable FPGA. It allows models to be executed on high-to-low or low-to-high transition events instead of being based on the CPU timer.

Speedgoat Simulink Programmable FPGAs come with interrupt generation support for the PWM generation FPGA code module by default. The standard interrupt implementation requires one input line and requests the interrupt (#intA) as defined in the provided Simulink Real-Time driver blockset. Other interrupt generation events can be implemented on request for the PWM and other code modules, for example when a tasks completes, reaches a specific stage, or an error occurs. Please contact us with your requirements.

Supported parameter settings

Debounce duration: defines the duration where the interrupt input signal is tested. If the signal is stable for the specifieds time, the FPGA declares it is a valid signal and asserts the interrupt. Enter '0' in this field to turn off the feature.

Interrupt delay: Optional delay before asserting the interrupt.

Polarity: the FPGA can assert the interrupt when the input signal is rising (value '0') or falling (value '1').

This code module is normally delivered as part of a custom implementation with your selection of functionality and I/O count. Please contact us for further information.

Pricing information
We don't publish pricing information on our website. Upon request by e-mail or phone we can provide a complete price list covering our entire product portfolio in various currencies. We recommend that you get in touch with us to discuss your specific needs. We can then quickly provide you with a tailored quotation including technical and pricing information.


Included in delivery

  • Delivered as part of a HDL Coder integration package configured to your requirements
  • Simulink driver block
  • Test models
  • Comprehensive documentation

Supported target machines


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