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Quadrature Decoder FPGA Code Module

Configurable Quadrature decoding support with Simulink driver block

This FPGA code module provides quadrature decoding support. By analyzing two 90 degrees shifted signal inputs from incremental encoder sensors, rotation direction and position can be determined.

The two signals A and B in the below graph represent typical waveforms of such inputs. Signal C/Index represents the end of each complete cycle:

Depending on your required data, the QAD code module allows you to set the following parameters:

Quadrature modes:

  • 1x: Counter increments at each rising edge event of signal A
  • 2x: Counter increments at each rising or falling edge event of signal A
  • 4x: Counter increments at each rising or falling edge event of signal A and B

Actions on Index (C)

You can define the following counter settings whenever C/Index is High (end of cycle):

  • Reset on index: Counter is cleared
  • Reload on index: Counter is reset with your selected init value
  • Latch on index: Stores the counter value into the output register
  • Index reference mode: Resets the counter to zero when the C/Index signal of the encoder is high for the first time. After this initial high C/Index signal, the QAD code module will ignore the C/Index signal and switch to "ignore index input" mode.
  • Ignore index input: no action

Counting modes

  • Cycling counter: defines a counter range of -2^31 to 2^31 - 1
  • Divide-by-N: defines a counter range of - Steps per revolution to + Steps per revolution - 1. Each time the counter reaches the selected minimum or maximum Steps per revolution value, the counter is reset.
  • Single Cycle: Counting stops when a defined counting value is met. To start counting again, a reset is required.

Steps per revolution

The number of steps can be freely configured based on your hardware specifications. Typical values are powers of two (1024, 2048, 4096, …).

A Quadrature encoder FPGA code module is also available.

Item ID Product Name Components
303MOT Motion Control HDL I/O Blockset
  • Simulink blocks and the corresponding VHDL files to use code module functionality in the HDL Coder workflow  
  • Simulink example model 
  • Simulink library for configuration and utility blocks 
  • Comprehensive documentation  
203XXA  Custom Implementation Package 
  • Project-specific FPGA bitstream implemented with the required number of code module channels 
  • Simulink example model 
  • Simulink library  
  • Comprehensive documentation   

This FPGA code module is normally delivered as part of a custom implementation with your selection of functionality and I/O count. Please contact us for further information.

Pricing information
We don't publish pricing information on our website. Upon request by e-mail or phone we can provide a complete price list covering our entire product portfolio in various currencies. We recommend that you get in touch with us to discuss your specific needs. We can then quickly provide you with a tailored quotation including technical and pricing information.


Included in delivery

For our configurable FPGA I/O modules, offered as part of a Custom Implementation Package: 

  • FPGA bitstream implemented according to customer requirements 
  • Simulink® example models 
  • Simulink library 
  • Comprehensive documentation 

For our Simulink-programmable FPGA I/O modules, offered as part of the Motion Control HDL I/O Blockset: 

  • Simulink blocks and the corresponding VHDL files to use code module functionality in the HDL Coder workflow 
  • Simulink library, a sample Simulink model and comprehensive documentation 

Supported I/O modules

  • All configurable and Simulink-programmable FPGA I/O modules featuring digital I/O lines  


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