This FPGA code module provides SPI sniffer support. This allows an existing SPI communication setup to be monitored.
SPI master and slave functionality is provided by the SPI FPGA code module.
An example timing diagram of the signal read by the SPI sniffer FPGA code module
T 1 = Start delay (master only)
T 2 = Clock divider
T 3 = Inter-word delay (master only)
T 4 = Stop delay (master only)