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SPI Sniffer FPGA Code Module

Configurable SPI Sniffer support with Simulink driver block

This FPGA code module provides SPI sniffer support. This allows an existing SPI communication setup to be monitored.

SPI master and slave functionality is provided by the SPI FPGA code module.

An example timing diagram of the signal read by the SPI sniffer FPGA code module

SPI FPGA code module timing diagram T 1 = Start delay (master only)
T 2 = Clock divider
T 3 = Inter-word delay (master only)
T 4 = Stop delay (master only)

Item ID Product Name Components
303SPI   HCFP-SPI
  • Simulink blocks and the corresponding VHDL files to use code module functionality in the HDL Coder workflow  
  • Simulink example model 
  • Simulink library for configuration and utility blocks 
  • Comprehensive documentation  
203XXA  Custom Implementation Package 
  • Project-specific FPGA bitstream implemented with the required number of code module channels 
  • Simulink example model 
  • Simulink library  
  • Comprehensive documentation   

This FPGA code module is normally delivered as part of a custom implementation with your selection of functionality and I/O count. Please contact us for further information.


Pricing information
We don't publish pricing information on our website. Upon request by e-mail or phone we can provide a complete price list covering our entire product portfolio in various currencies. We recommend that you get in touch with us to discuss your specific needs. We can then quickly provide you with a tailored quotation including technical and pricing information.

 

Included in delivery

For our configurable FPGA I/O modules, offered as part of a Custom Implementation Package: 

  • FPGA bitstream implemented according to customer requirements 
  • Simulink® example models 
  • Simulink library 
  • Comprehensive documentation 

For our Simulink-programmable FPGA I/O modules, offered as part of a HDL Coder Functionality Package: 

  • Simulink blocks and the corresponding VHDL files to use code module functionality in the HDL Coder workflow 
  • Simulink library, a sample Simulink model and comprehensive documentation 

Supported I/O modules

  • All configurable and Simulink-programmable FPGA I/O modules featuring digital I/O lines  

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