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Documentation
CONTENTS
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Examples

Examples — Dedicated examples are included for testing the HDL interface functionality

Introduction

To test the HDL interface functionality, dedicated examples are included in the downloaded archive file. To open the examples, navigate to the corresponding folder. Note that the examples only test I/O channels for which the loopback test method is possible. The terminal board provided must be wired as described. Examples do not test I/O channels that require external hardware (for some examples a function generator or an oscilloscope is required), but running this example will still provide sufficient confirmation of the correct setup of this implementation. The examples only test interface channels which are provided by the base functionality of the I/O module. Please note that the examples provided have been color coded. The green colored subsystem (FPGA domain) is the part of the model which is actually compiled using HDL Coder and ultimately runs on the FPGA. The FPGA domain usually has a sample frequency in the range of 100 MHz and is set in the HDL Workflow Advisor (FPGA Synthesis Software Settings). The blue blocks (CPU domain) which surround the green subsystem are interfaces to the processor section of the model. The CPU domain usually has a sample frequency in the range of 1 kHz. The interrupt subsystem has been given another color (magenta), as its functionality is asynchronous to both the processor and FPGA. The interrupt source can be selected in the generated model in the Interrupt Setup block once the model has been run through the HDL Coder Workflow Advisor.

Fundamentals

IO3xx BaseExample showcasing the PCIe interface and interrupt interface
IO3xx Direct StreamExample showcasing data directly streamed out of the design under test (DUT) through the DMA engine and PCIe Endpoint to the system memory
IO3xx Playback Example Example showcasing playback DMA functionality with data originated in the CPU and sampled out with a fixed sample rate on the FPGA.
IO3xx Coprocessor ExampleExample showcasing several implementations of coprocessor DMA engine handling.
IO3xx Ring Buffer ExampleExample Showcasing a ring buffer on the FPGA as well as the DMA data path to the CPU domain

IO3xx Rear Plug-ins

IO33x-21Example showcasing the rear interface.
IO342-21Example showcasing the rear interface.
IO33x-22Example showcasing the rear interface
IO342-22Example showcasing the rear interface
IO3xx-32Example showcasing the SFP interface

IO33x Front Plug-ins

IO33x-01LVExample showcasing the front interface
IO33x-02Example showcasing the front interface
IO33x-03Example showcasing the front interface
IO33x-04Example showcasing the front interface
IO33x-06Example showcasing the front interface
IO33x-07Example showcasing the front interface
IO33x-08Example showcasing the front interface

IO333-SFP

IO333-SFP LVCMOS/LVDSExample showcasing the front DIO interface
IO333-SFP Aurora SFPExample showcasing the front SFP interface
IO333-SFP Video SFPExample Showcasing a Complete Data Path for a Video Signal through the FPGA.

IO334

IO334 analog input and analog outputExample showcasing the analog input and analog output interface
IO334 HIL (pre-built)Pre-built example ready to be deployed to the hardware showcasing the analog input and analog output interface and FPGA Code Module functionality such as PWM capture (CAP), Quadrature encoding (QAE) and Interrupts
IO334 RCP (pre-built)Pre-built example ready to be deployed to the hardware showcasing the analog input and analog output interface and FPGA Code Module functionality such as PWM generation, Quadrature decoding (QAD) and Interrupts

IO335

IO335 analog outputExample showcasing the analog input and differential input interface

IO342

IO342-21Example showcasing the rear interface.
IO342-22Example showcasing the rear interface
IO342-51Example showcasing the Aurora interface.
IO342-63 analog input to RAM to CDMAExample showcasing the front interface
IO342-63-63 analog input to RAM to CDMAExample showcasing the dual front interface

IO397

IO397 analog input, analog output and TTLExample showcasing the front analog input, analog output and TTL interfaces.