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Speedgoat IO342-51 Example

Speedgoat IO342-51 Example — Example showcasing the Aurora interface.

Model Name

The model is called IO342_51_64B66B_hdlc.slx.

Supported Modules

  • IO342-1450k, IO342-1080k

Required Toolboxes

The list of basic software requirements are provided in the prerequisites section of the Getting Started page.


The IO342-51 example uses the following interfaces:

User Blocks

The example does not utilize any user blocks.


To test the HDL interface functionality, dedicated examples are included in the downloaded archive file. To open the examples, navigate to the corresponding folder. Note that the examples only test I/O channels for which the loopback test method is possible. The terminal board provided must be wired as described. Examples do not test I/O channels that require external hardware (for some examples a function generator or an oscilloscope is required), but running this example will still provide sufficient confirmation of the correct setup of this implementation. The examples only test interface channels which are provided by the base functionality of the I/O module. Please note that the examples provided have been color coded. The green colored subsystem (FPGA domain) is the part of the model which is actually compiled using HDL Coder and ultimately runs on the FPGA. The FPGA domain usually has a sample frequency in the range of 100 MHz and is set in the HDL Workflow Advisor (FPGA Synthesis Software Settings). The blue blocks (CPU domain) which surround the green subsystem are interfaces to the processor section of the model. The CPU domain usually has a sample frequency in the range of 1 kHz. The interrupt subsystem has been given another color (magenta), as its functionality is asynchronous to both the processor and FPGA. The interrupt source can be selected in the generated model in the Interrupt Setup block once the model has been run through the HDL Coder Workflow Advisor.

Open the example model by navigating to the folder containing the "*.slx" model file and double clicking the file. If the example is provided as a Simulink Project, navigate to the corresponding example folder and extract the Simulink project zip file. Then double-click the "*.prj" icon to open the project. After opening the project, open the model by double clicking the "*.slx" file. The model is shown as follows:

The DUT_51_64B66B subsystem is shown as follows:

Test Wiring

Use the following test wiring to ensure the correct functionality of the example provided. Alternatively, a multi-mode fibre loopback module (for example 12-Fibers MTP/MPO Female Type 1 LSZH OM3 50/125) can be used.

From PinTo PinTested Functionality
Port 0 (Lane 1)Port 0 (Lane 1)Aurora Tx to Aurora Rx
Port 0 (Lane 2)Port 0 (Lane 2)Aurora Tx to Aurora Rx
Port 0 (Lane 3)Port 0 (Lane 3)Aurora Tx to Aurora Rx
Port 0 (Lane 4)Port 0 (Lane 4)Aurora Tx to Aurora Rx
Port 1 (Lane 1)Port 1 (Lane 1)Aurora Tx to Aurora Rx
Port 1 (Lane 2)Port 1 (Lane 2)Aurora Tx to Aurora Rx
Port 1 (Lane 3)Port 1 (Lane 3)Aurora Tx to Aurora Rx
Port 1 (Lane 4)Port 1 (Lane 4)Aurora Tx to Aurora Rx

Running HDL Workflow Advisor

Before the example can be deployed and run on the real-time target machine, you will need to run through the HDL Coder Workflow Advisor steps to actually generate HDL code and a FPGA bitstream using HDL Coder (FPGA Synthesis Software Settings).

New: Reference design parameters, set at step 1.2 now control which interfaces will be available to target in step 1.3 of the workflow. This has reduced the total number of reference designs, and the list of interfaces available. Please remember to select the front plug-in and rear plug-in setting that is appropriate for your module, as well as the Aurora settings that should be used for your model (if applicable). These additional reference design parameter settings are further described in the interface sections for which they are relevant.

New: Prior to running the workflow advisor, be sure to double click the Select Module block in the demo model. If one or more of your modules support the model (due to available interface compatibility), a pop-up will display prompting you to select the module you would like to target. If only a single module is installed, and providing it is compatible, it will be automatically selected when the box is double clicked.

Upon completion, a newly generated model containing the Simulink Real-Time interface subsystem appears. At first sight, this subsystem resembles the FPGA subsystem. However, inside, the Simulink algorithm has been removed and replaced with blocks that the real-time application will use to communicate with the FPGA during simulation execution. The newly generated model is now ready to be deployed to a real-time target machine. To download the FPGA bitstream and the Simulink model to the target, click the Build Model button on the Simulink Editor toolbar. The real-time application loads on the Speedgoat target machine and the FPGA algorithm bitstream loads on the FPGA. If you are using I/O lines, check that you have connected the lines to the external hardware under test. Please note that some example models do have Global Delay Balancing intentionally disabled. If an error is displayed about delay balancing in step 2.3 of the HDL Coder Workflow Advisor, it can be safely ignored by checking the Ignore warnings checkbox.

Real-Time Simulation Outputs

Once the model has been downloaded and the target application has started, double-click the scope to see the following traces:

  • "Scope Data"

    • Display IO342_51_CNTR_TX_RX_DIFF shows the numerical propagation delay of the Aurora 64b/66b chain measured in FPGA ticks

    • Display IO342_51_CRC_PASS_VALID_DIFF shows the difference of the crc pass and crc valid counters

    • Display IO342_51_SINUSOIDALS shows the sinusoidal received and transmitted

  • "Scope Status" shows the Aurora Status Register. There is one Display for each of the eight Aurora channels