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Speedgoat IO342-63-63 A/D to RAM to CDMA Example

Speedgoat IO342-63-63 A/D to RAM to CDMA Example — Example showcasing the dual front interface

Model Name

The model is called IO342_63_63_ADC2RAM2CDMA_hdlc.slx.

Supported Modules

  • IO342-1450k-63-63

Required Toolboxes

The list of basic software requirements are provided in the prerequisites section of the Getting Started page.

In addition, you must also install the DSP System Toolbox.


The IO342-63-63 A/D to RAM to CDMA example uses the following interfaces:

User Blocks

The example uses the following user blocks:


To test the HDL interface functionality, dedicated examples are included in the downloaded archive file. To open the examples, navigate to the corresponding folder. Note that the examples only test I/O channels for which the loopback test method is possible. The terminal board provided must be wired as described. Examples do not test I/O channels that require external hardware (for some examples a function generator or an oscilloscope is required), but running this example will still provide sufficient confirmation of the correct setup of this implementation. The examples only test interface channels which are provided by the base functionality of the I/O module. Please note that the examples provided have been color coded. The green colored subsystem (FPGA domain) is the part of the model which is actually compiled using HDL Coder and ultimately runs on the FPGA. The FPGA domain usually has a sample frequency in the range of 100 MHz and is set in the HDL Workflow Advisor (FPGA Synthesis Software Settings). The blue blocks (CPU domain) which surround the green subsystem are interfaces to the processor section of the model. The CPU domain usually has a sample frequency in the range of 1 kHz. The interrupt subsystem has been given another color (magenta), as its functionality is asynchronous to both the processor and FPGA. The interrupt source can be selected in the generated model in the Interrupt Setup block once the model has been run through the HDL Coder Workflow Advisor.

Open the example model by navigating to the folder containing the "*.slx" model file and double clicking the file. If the example is provided as a Simulink Project, navigate to the corresponding example folder and extract the Simulink project zip file. Then double-click the "*.prj" icon to open the project. After opening the project, open the model by double clicking the "*.slx" file. The model is shown as follows:

The test model supplied consists of a data path for logging a sequential set of analog input samples. As a convenience, the model includes the DDS signal generators from the DDS test model, which can act as a loopback source for the analog input channels. The analog input channel being recorded can be set by changing the constant value being fed into "PCIe_ADC_INDEX". As in the DDS model, the analog output loopback signals can be modified by changing the constant values stored in the "DAC Frequencies" and "DAC Amplitudes) constant blocks.

The signal capture path moves the analog input from the analog input ports into a small FIFO. The FIFO exists to buffer the input data during the clock cycles when the AXI4 Master interface is not prepared to accept samples. After the FIFO, the samples are fed directly into an AXI4 Master port. The implementation of the AXI4 Master port is very straightforward; the model defines a start address (0x0) and a number of samples to be written to the RAM (stored in the data dictionary, in the "RAMBufferBytes" variable). After the RAM has been filled by a set of consecutive samples, the CPU portion of the model is signaled using the falling edge on the "PCIe_RAM_Buffer_Filling" port. At this point, the FPGA RAM Frame Buffer block is allowed to read the samples from the RAM over the course of several model executions. From the output of this block, the data values can be captured using the SDI (Signal Data Inspector) signal logging system. The model execution is very fast, requiring only 145 time steps to complete the full transaction. Once the model execution is complete, the data is analyzed.

The data path provided can be used as a starting point for a general purpose data capture application. The script provided shows how the behavior of the model is controlled using programmable parameters. The results are captured using the SDI logging subsystem.

Test Wiring

Use the following test wiring for both FMC slots to ensure the correct functionality of the test model provided.

CoaxTested Functionality
A0-D0Analog input is being fed by the analog output.
A1-D1Analog input is being fed by the analog output.
A2-D2Analog input is being fed by the analog output.
A3-D3Analog input is being fed by the analog output.

As an alternative to loop-back, an external signal could also be supplied to the A0-A3 inputs. Please take care not to exceed the maximum amplitude of the inputs as described in the interfaces section.

Running HDL Workflow Advisor

Before the example can be deployed and run on the real-time target machine, you will need to run through the HDL Coder Workflow Advisor steps to actually generate HDL code and a FPGA bitstream using HDL Coder (FPGA Synthesis Software Settings).

New: Reference design parameters, set at step 1.2 now control which interfaces will be available to target in step 1.3 of the workflow. This has reduced the total number of reference designs, and the list of interfaces available. Please remember to select the front plug-in and rear plug-in setting that is appropriate for your module, as well as the Aurora settings that should be used for your model (if applicable). These additional reference design parameter settings are further described in the interface sections for which they are relevant.

New: Prior to running the workflow advisor, be sure to double click the Select Module block in the demo model. If one or more of your modules support the model (due to available interface compatibility), a pop-up will display prompting you to select the module you would like to target. If only a single module is installed, and providing it is compatible, it will be automatically selected when the box is double clicked.

Upon completion, a newly generated model containing the Simulink Real-Time interface subsystem appears. At first sight, this subsystem resembles the FPGA subsystem. However, inside, the Simulink algorithm has been removed and replaced with blocks that the real-time application will use to communicate with the FPGA during simulation execution. The newly generated model is now ready to be deployed to a real-time target machine. To download the FPGA bitstream and the Simulink model to the target, click the Build Model button on the Simulink Editor toolbar. The real-time application loads on the Speedgoat target machine and the FPGA algorithm bitstream loads on the FPGA. If you are using I/O lines, check that you have connected the lines to the external hardware under test. Please note that some example models do have Global Delay Balancing intentionally disabled. If an error is displayed about delay balancing in step 2.3 of the HDL Coder Workflow Advisor, it can be safely ignored by checking the Ignore warnings checkbox.

Real-Time Simulation Outputs

To launch the simulation, run the IO34x_63_63_ADC2RAM2CDMA_hdlc_run.m script. The script will correctly parameterize and run the generated model, and then analyze the results.

IO34x_63_63_ADC2RAM2CDMA_hdlc.slx measured signal characteristics (10 MHz input signal).

The model behavior can easily be changed by modifying the analog input channel constant and/or the analog output frequency and amplitude values. By manually modifying these values between runs of the script provided, each channel of the analog input and analog output can be tested.

The qualitative results of the user measurement will vary from the above diagram, depending on the input signals used. The lower of the two plots shows details of the low frequency performance. This model tests the performance of the analog input channels and provides a starting point for a customer-specific data capture application.