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Documentation
CONTENTS

Speedgoat AXI4 Master Interface

Speedgoat AXI4 Master Interface — Allows the FPGA to read and write to external RAM

Supported Modules

  • IO332-200k

  • IO333-325k, IO333-410k, IO333-325k-SFP, IO333-410k-SFP

  • IO334-325k, IO335-325k

  • IO342-1450k, IO342-1080k

Simplified AXI4 Master Interface

For writing and reading to the external RAM, the standard AXI4 Master interface connects from the design under test (DUT) to the memory controller. Further information on the simplified AXI4 Master interface and its modeling aspects can be found on the MathWorks documentation page: Model Design for AXI4 Master Interface Generation.

AXI4 Master External RAM Write

The design under test (DUT) waits for wr_ready to become high to initiate a write request. When wr_ready becomes high, the DUT can send out the write request. The write request consists of the Data and Write Master to Slave bus signals. This bus consists of wr_len, wr_addr and wr_valid. wr_addr specifies the starting address to which DUT wants to write. The wr_len signal corresponds to the number of data elements in this write transaction. Data can be sent as long as wr_valid is high. When wr_ready becomes low, the DUT must stop sending data within one clock cycle, and the Data signal becomes invalid. If the DUT continues to send data after one clock cycle, the data is ignored.

InputOutput
wr_ready (Write Slave to Master bus)

This signal corresponds to the backpressure from the external memory. When this control signal goes high, it indicates that data can be sent. When wr_ready is low, the DUT must stop sending data within one clock cycle. You can also use the wr_ready signal to determine whether the DUT can send a second burst signal immediately after the first burst signal has been sent. Multiple burst signals are supported, which means that the wr_ready signal remains high to accept the second burst immediately after the last element of the first burst has been accepted.

  • Data Type: boolean

wr_bvalid (Write Slave to Master bus, optional)

Response signal from the external memory that you can use for diagnosis purposes. The wr_bvalid signal becomes high after the AXI4 interconnect accepts each burst transaction. If wr_len is greater than 256, the AXI4 Master write module splits the large burst signal into 256-sized bursts. wr_bvalid becomes high for each 256-sized burst.

  • Data Type: boolean

wr_bresp (Write Slave to Master bus, optional)

Response signal from the external memory that you can use for diagnosis purposes. The wr_bvalid signal becomes high after the AXI4 interconnect accepts each burst transaction. If wr_len is greater than 256, the AXI4 Master write module splits the large burst signal into 256-sized bursts. wr_bvalid becomes high for each 256-sized burst.

  • Data Type: boolean

wr_complete (Write Slave to Master bus, optional)

Control signal which when high for one clock cycle indicates that the write transaction has completed. This signal asserts at the last wr_bvalid of the burst.

  • Data Type: boolean

Data

The data that you want to transfer is valid for each cycle of the transaction.

  • Data Type: Between fixdt(0,8,0) and fixdt(0,128,0)

wr_addr (Write Master to Slave bus)

Starting address of the write transaction that is sampled at the first cycle of the transaction.

  • Data Type: uint32

wr_len (Write Master to Slave bus)

The number of data values that you want to transfer, sampled at the first cycle of the transaction.

  • Data Type: uint32

wr_valid (Write Master to Slave bus)

When this control signal becomes high, it indicates that the Data signal sampled at the output is valid.

  • Data Type: boolean

AXI4 Master External RAM Read

The design under test (DUT) waits for rd_aready to become high to initiate a read request. When rd_aready is high, the DUT can send out the read request. The read request consists of the rd_addr, rd_len and rd_avalid signals of the Read Master to Slave bus. The external memory responds to the read request by sending the Data at each clock cycle. The rd_len signal corresponds to the number of data values to read. The DUT can receive data as long as rd_dvalid is high.

InputOutput
Data

The data that is returned from the read request.

  • Data Type: Data Type: Between fixdt(0,8,0) and fixdt(0,128,0)

rd_aready (Read Slave to Master bus)

This signal indicates when to accept read requests. You can monitor the rd_aready signal to determine whether the DUT can send consecutive burst requests. When rd_aready becomes high, it indicates that the DUT can send a read request in the next clock cycle.

  • Data Type: boolean

rd_dvalid (Read Slave to Master bus)

Control signal which indicates that the data returned from the read request is valid.

  • Data Type: boolean

rd_rvalid (Read Slave to Master bus, optional)

Response signal from the external memory that you can use for diagnosis purposes.

  • Data Type: boolean

rd_rresp (Read Slave to Master bus, optional)

Response signal from the external memory core that indicates the status of the read transaction.

  • Data Type: boolean

rd_addr (Read Master to Slave bus)

Starting address for the read transaction that is sampled at the first cycle of the transaction.

  • Data Type: uint32

rd_len (Read Master to Slave bus)

The number of data values that you want to read, sampled at the first cycle of the transaction.

  • Data Type: uint32

rd_avalid (Read Master to Slave bus)

Control signal that specifies whether the read request is valid.

  • Data Type: bus

rd_dready (Read Master to Slave bus, optional)

Control signal which indicates that the Data returned from the read request is valid.

  • Data Type: boolean

Interface Pin Mapping

There is no interface pin mapping.

Terminal Board

This interface does not require a terminal board.