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Documentation
CONTENTS

Speedgoat AXI4-Stream Interface

Speedgoat AXI4-Stream Interface — Allows the FPGA to read and write to the design under test (DUT) leveraging DMA

Supported Modules

  • IO332-200k

  • IO333-325k, IO333-410k, IO333-325k-SFP, IO333-410k-SFP

  • IO334-325k, IO335-325k

  • IO342-1450k, IO342-1080k

AXI4-Stream Interface

With the HDL Coder software, you can implement a simplified, streaming protocol in your model. The software generates AXI4-Stream interfaces in the IP core. The standard AXI4-Stream interface can be used to connect from the DUT to the DMA engine. The signals of the AXI4-Stream interface are described below. Further information on the AXI4-Stream interface and its modelling aspects can be found on the following MathWorks documentation page: Model Design for AXI4-Stream Interface Generation.

AXI4-Stream FPGA to CPU Master

InputOutput
Ready (optional)

The AXI4-Stream interfaces in your DUT can optionally include a Ready signal. In the Master interface, the Ready signal enables you to respond to backpressure. If you model the Ready signal in your AXI4-Stream interfaces, your Master interface must deassert its Valid signal one cycle after the Ready signal is deasserted. If you do not model the Ready signal, the HDL Coder generates the signal and the associated backpressure logic.

  • Data Type: boolean

Data

The data that you want to transfer, valid each cycle of the transaction.

  • Data Type: uint32

Valid

When this control signal becomes high, it indicates that the Data signal sampled at the output is valid.

  • Data Type: boolean

TLAST (optional)

This control signal indicates the boundary of a data package (or frame). If this signal is not implemented, HDL Coder will generate a programmable register in the IP Core so that the packet size can be configured from the CPU domain using software.

  • Data Type: boolean

TKEEP (optional)

This control signal indicates the number of valid bytes in the final data word of each frame.

  • Data Type: maximum bit width 16

AXI4-Stream CPU-to-FPGA Slave

InputOutput
Data

The data that you want to transfer, valid each cycle of the transaction.

  • Data Type: uint32

Valid

When this control signal becomes high, it indicates that the data signal sampled at the output is valid.

  • Data Type: boolean

TLAST (optional)

This control signal indicates the boundary of a data package (or frame). If this signal is not implemented, HDL Coder will generate a programmable register in the IP core so that the packet size can be configured from the CPU domain using software.

  • Data Type: boolean

TKEEP (optional)

This control signal indicates the number of valid bytes in the final data word of each frame.

  • Data Type: maximum bit width 16

Ready (optional)

The AXI4-Stream interfaces in your DUT can optionally include a Ready signal. In a Slave interface, the Ready signal enables you to apply backpressure. If you model the Ready signal in your AXI4-Stream interfaces, your Master interface must deassert its Valid signal one cycle after the Ready signal is deasserted. If you do not model the Ready signal, the HDL Coder generates the signal and the associated backpressure logic.

  • Data Type: boolean

Interface Pin Mapping

There is no interface pin mapping.

Terminal Board

This interface does not require a terminal board.