Supported Modules

LVCMOS Interface

X5 LVCMOS Channel [0:7]

X6 LVCMOS Channel [0:7]

The I/O module provides up to 16 LVCMOS25 I/O lines.

LVDS Interface

X5 LVDS Channel [0:3]

X6 LVDS Channel [0:3]

The I/O module provides up to 8 LVDS_25 I/O lines.

Aurora - General Introduction

Aurora is a scalable, lightweight, link-layer communications protocol that is used to move data across point-to-point serial links. It provides a transparent interface to the physical layer, allowing upper layers of proprietary or industry-standard protocols to easily use high-speed transceivers. Our abstraction layer utilizes the Xilinx Aurora standard to provide an interface which can be used in your HDL-Coder-based models for high speed data transfer into and out of the model. There are two encoding standards (depending on the FPGA, only one might be implemented), 64b/66b and 8b/10b allowing easy connection to AXI4-Stream-compliant IP designs. The default Aurora IP core configuration is in little endian support [n:0]. 8b/10b (64b/66b) is a line code that transforms 8-bit (64-bit) data to 10-bit (66-bit) line code to provide enough state changes to allow reasonable clock recovery and alignment of the data stream at the receiver side. The overhead of 64b/66b encoding is 2 coding bits for every 64 payload bits or 3.125 %. This is considerably more efficient than the 25 % overhead of the 8b/10b encoding scheme, which adds 2 coding bits to every 8 payload bits. However the latency is considerably higher with 64b/66b than with 8b/10b. Depending on your I/O module and HDL Coder Integration Package, line rates from 3.125 to 12.5 Gbps and the selection of desired encoding scheme are available as reference design parameters in the HDL Workflow Advisor at step 1.2. As Aurora interconnects are used for module to module communication, ensure that design parameters are chosen consistently across both designs that are to be connected.

For more information about the AXI4-Stream interface, refer also to the MathWorks Model Design for AXI4-Stream Interface Generation documentation and to the Xilinx UG1037 AXI reference guide. For more information about Aurora IP, refer to Xilinx PG074 Aurora 64B/66B reference guide and PG046 Aurora 8B/10B reference guide.

Propagation delays and supported I/O modules for Aurora 64b/66b (64-bit beat) are:

Propagation delays and supported I/O modules for Aurora 8b/10b (32-bit beat) are:

Reference Design Parameters

Be sure to select appropriate reference design parameters in step 1.2 of the workflow for your design so that the correct settings are in place for your intended use of the Aurora interface. Two pull-down menus are included. The first lets you select the line rate and encoding scheme that you would like to use, and the second allows the endianness of the interface to be set.

Aurora Interface

Aurora X5 - Stream

Aurora X6 - Stream

The IO333 I/O module features eight internal Aurora ports. They can be used to transfer AXI4-Stream via multi-gigabit transceivers (MGT). The interface leverages the Speedgoat AXI4 Stream Interface.

Aurora Reset Push Button

The Aurora interface provides a software reset push button to reset the Aurora IP core. There is one reset push button per Aurora channel.

Bits 13-15 of the Aurora initialization status are described below:

Interface Pin Mapping

The LVCMOS/LVDS pin mapping is as follows:

The pin mapping for the Aurora streams is as follows:

Terminal Board

This interface does not require a terminal board.