Skip to main content

Customer Login

This content is for Speedgoat customer only. Log in to see content.

Forgot your password?

Don't have a Speedgoat account? Create an account.

Documentation
CONTENTS

Speedgoat IO333-SFP Aurora Interface

Speedgoat IO333-SFP Aurora Interface — Interface with four Aurora streams

Supported Modules

  • IO333-325k-SFP, IO333-410k-SFP

LVCMOS Interface

X5 LVCMOS Channel [0:7]

X6 LVCMOS Channel [0:7]

The I/O module provides up to 16 LVCMOS25 I/O lines.

  • Data Type: boolean

  • Direction: input/output

LVDS Interface

X5 LVDS Channel [0:3]

X6 LVDS Channel [0:3]

The I/O module provides up to 8 LVDS_25 I/O lines.

  • Data Type: boolean

  • Direction: input/output

Aurora - General Introduction

Aurora is a scalable, lightweight, link-layer communications protocol that is used to move data across point-to-point serial links. It provides a transparent interface to the physical layer, allowing upper layers of proprietary or industry-standard protocols to easily use high-speed transceivers. Our abstraction layer utilizes the Xilinx Aurora standard to provide an interface which can be used in your HDL-Coder-based models for high speed data transfer into and out of the model. There are two encoding standards (depending on the FPGA, only one might be implemented), 64b/66b and 8b/10b allowing easy connection to AXI4-Stream-compliant IP designs. The default Aurora IP core configuration is in little endian support [n:0]. 8b/10b (64b/66b) is a line code that transforms 8-bit (64-bit) data to 10-bit (66-bit) line code to provide enough state changes to allow reasonable clock recovery and alignment of the data stream at the receiver side. The overhead of 64b/66b encoding is 2 coding bits for every 64 payload bits or 3.125 %. This is considerably more efficient than the 25 % overhead of the 8b/10b encoding scheme, which adds 2 coding bits to every 8 payload bits. However the latency is considerably higher with 64b/66b than with 8b/10b. Depending on your I/O module and HDL Coder Integration Package, line rates from 3.125 to 12.5 Gbps and the selection of desired encoding scheme are available as reference design parameters in the HDL Workflow Advisor at step 1.2. As Aurora interconnects are used for module to module communication, ensure that design parameters are chosen consistently across both designs that are to be connected.

For more information about the AXI4-Stream interface, refer also to the MathWorks Model Design for AXI4-Stream Interface Generation documentation and to the Xilinx UG1037 AXI reference guide. For more information about Aurora IP, refer to Xilinx PG074 Aurora 64B/66B reference guide and PG046 Aurora 8B/10B reference guide.

Propagation delays and supported I/O modules for Aurora 64b/66b (64-bit beat) are:

Line RatePropagation Delay (64-bit beat)Minimal DUT FrequencyAurora User Clock (user_clk)Supported I/O Modules
3.125 Gbps1.6 µs50 MHz48.828125 MHzIO333-325k, IO333-325k-SFP, IO333-410k, IO333-410k-SFP, IO334-325k, IO335-325k, IO342-1080k, IO342-1450k
5 Gbps1.1 µs80 MHz78.125 MHz
10 Gbps0.5 µs160 MHz156.25 MHzIO342-1080k, IO342-1450k
12.5 Gbps0.4 µs200 MHz 195.3125 MHzIO342-1080k, IO342-1450k

Propagation delays and supported I/O modules for Aurora 8b/10b (32-bit beat) are:

Line RatePropagation Delay (32-bit beat)Minimal DUT FrequencyAurora User Clock (user_clk)Supported I/O Modules
3.125 Gbps0.9 µs80 MHz78.125 MHzIO332-200k, IO333-325k, IO333-325k-SFP, IO333-410k, IO333-410k-SFP, IO334-325k, IO335-325k, IO342-1080k, IO342-1450k
5 Gbps0.7 µs130 MHz125 MHz

Reference Design Parameters

Be sure to select appropriate reference design parameters in step 1.2 of the workflow for your design so that the correct settings are in place for your intended use of the Aurora interface. Two pull-down menus are included. The first lets you select the line rate and encoding scheme that you would like to use, and the second allows the endianness of the interface to be set.

Aurora Interface

Aurora X5 - Stream

Aurora X6 - Stream

The IO333-SFP features four internal Aurora ports. They can be used to transfer AXI4-stream via multi-gigabit transceivers (MGT). The interface leverages the Speedgoat AXI4 Stream Interface.

  • Aurora stream 1 is located at carrier connector X5/P2

  • Aurora stream 2 is located at carrier connector X5/P2

  • Aurora stream 3 is located at carrier connector X6/P3

  • Aurora stream 4 is located at carrier connector X6/P3

Aurora Reset Push Button

The Aurora interface provides a software reset push button to reset the Aurora IP core. There is one reset push button per Aurora channel.

  • Data Type: boolean

  • Direction: output

Aurora Status Register

The Aurora interface provides a status register of the Aurora IP core. There is one status register per Aurora channel.

  • Data Type: uint16

  • Direction: input

BitStatus Register FireflyStatus Register SFPStatus Register QSFPDefault Value
0Channel upChannel upChannel up0
1Lane upLane upLane up0
2:3n.c.n.c.n.c.GND
4Hardware errorHardware errorHardware error0
5Software errorSoftware errorSoftware error0
6:7n.c.n.c.n.c.GND
8CRC pass fail notCRC pass fail notCRC pass fail not0
9CRC validCRC validCRC valid0
10PoweredSFP signal detect notPowered1
11Present notSFP Tx faultPresent not1
12n.c.SFP present notn.c.GND/1/GND
13:15Aurora initialization statusAurora initialization statusAurora initialization status0x7

Bits 13-15 of the Aurora initialization status are described below:

Bits 13-15Initialization Status
0x0Power up
0x1Wait for PLL to lock
0x2PMA initialization delay
0x3Running
0x4Initialization
0x5Reset
0x6Power on reset
0x7Fast reset

Interface Pin Mapping

The LVCMOS/LVDS pin mapping is as follows:

FireFly UEC5 PinData TypeTarget Platform InterfacesBit Range Address FPGA Pin
9 (A)booleanX5 LVCMOS Channel [0:7]0
X5 LVDS Channel [0:3]0 (+)
8 (A)booleanX5 LVCMOS Channel [0:7]1
X5 LVDS Channel [0:3]0 (-)
9 (B)booleanX5 LVCMOS Channel [0:7]2
X5 LVDS Channel [0:3]1 (+)
8 (B)booleanX5 LVCMOS Channel [0:7]3
X5 LVDS Channel [0:3]1 (-)
11 (A)booleanX5 LVCMOS Channel [0:7]4
X5 LVDS Channel [0:3]2 (+)
12 (A)booleanX5 LVCMOS Channel [0:7]5
X5 LVDS Channel [0:3]2 (-)
11 (B)booleanX5 LVCMOS Channel [0:7]6
X5 LVDS Channel [0:3]3 (+)
12 (B)booleanX5 LVCMOS Channel [0:7]7
X5 LVDS Channel [0:3]3 (-)
FireFly UEC5 PinData TypeTarget Platform InterfacesBit Range Address FPGA Pin
9 (A)booleanX6 LVCMOS Channel [0:7]0
X6 LVDS Channel [0:3]0 (+)
8 (A)booleanX6 LVCMOS Channel [0:7]1
X6 LVDS Channel [0:3]0 (-)
9 (B)booleanX6 LVCMOS Channel [0:7]2
X6 LVDS Channel [0:3]1 (+)
8 (B)booleanX6 LVCMOS Channel [0:7]3
X6 LVDS Channel [0:3]1 (-)
11 (A)booleanX6 LVCMOS Channel [0:7]4
X6 LVDS Channel [0:3]2 (+)
12 (A)booleanX6 LVCMOS Channel [0:7]5
X6 LVDS Channel [0:3]2 (-)
11 (B)booleanX6 LVCMOS Channel [0:7]6
X6 LVDS Channel [0:3]3 (+)
12 (B)booleanX6 LVCMOS Channel [0:7]7
X6 LVDS Channel [0:3]3 (-)

The pin mapping for the Aurora streams is as follows:

ConnectorTarget Platform InterfacesLane
X5/P2Aurora X5 - Stream 1 MasterLane 0
Aurora X5 - Stream 1 Slave
X5/P2Aurora X5 - Stream 2 MasterLane 1
Aurora X5 - Stream 2 Slave
X6/P3Aurora X6 - Stream 3 MasterLane 0
Aurora X6 - Stream 3 Slave
X6/P3Aurora X6 - Stream 4 MasterLane 1
Aurora X6 - Stream 4 Slave

Terminal Board

This interface does not require a terminal board.