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Documentation
CONTENTS

Speedgoat IO33x-07 Interface

Speedgoat IO33x-07 Interface — Front interface with 16x 16-bit analog outputs

Supported Modules

  • IO332-200k

  • IO333-325k, IO333-410k

Reference Design Parameters

Be sure to select "-07" as your reference design's front plugin using the pulldown menu at step 1.2 of the workflow advisor so that the appropriate interfaces will be available in step 1.3 of the workflow.

D/A Interface

D/A Output Channel [0:15]

The IO33x-07 I/O module features 4 LTC2755 D/A converters, providing a total of sixteen 16-bit channels. The IO33x-07 writes in sequences: each write of an active channel consumes four FPGA ticks, whereas an inactive channel consumes only one FPGA tick. There is a constant overhead of six ticks when the D/A Group Trigger is detected and all the channels are updated. Therefore, if all the channels are active, all the channels will be updated 70 ticks after the rising edge of the D/A Group Trigger.

  • Data Type: int16

  • Direction: output

DescriptionD/A Output Voltage (Range ±10)Digital Code
Full Scale Range (FSR)20 V-
Least Significant Bit (LSB)305.18 µV-
Full Scale (positive)9.999695 V0x7FFF
FSR - 1 LSB9.999390 V0x7FFE
Mid-scale + 1 LSB305 µV0x0001
Mid-scale0.0 V0x0000
Mid-scale - 1LSB-305 µV0xFFFF
-FSR + 1LSB-9.999695 V0x8001
Full Scale (negative)-10 V0x8000

D/A Group Trigger [0]

This port can trigger all 16 channels simultaneously. The trigger port is level-sensitive, meaning that if a constant high is applied to the port, the D/A converters are updated with the maximum frequency. To obtain a synchronized setup, model the D/A Group Trigger with ideally a single clock pulse of the FPGA target frequency. In addition, the generation of the required D/A signal must be synchronized with the D/A Group Trigger signal. If not, you might encounter a jitter of one D/A Group Trigger cycle.

  • Data Type: boolean

  • Direction: output

Interface Pin Mapping

The pin mapping for the IO33x-07 front plug-in is as follows:

Terminal PinData TypeTarget Platform InterfacesBit Range Address FPGA Pin
1int16D/A Output Channel [0:15]0
2int16D/A Output Channel [0:15]1
3int16D/A Output Channel [0:15]2
4int16D/A Output Channel [0:15]3
5int16D/A Output Channel [0:15]4
6int16D/A Output Channel [0:15]5
7int16D/A Output Channel [0:15]6
8int16D/A Output Channel [0:15]7
9int16D/A Output Channel [0:15]8
10int16D/A Output Channel [0:15]9
11int16D/A Output Channel [0:15]10
12int16D/A Output Channel [0:15]11
13int16D/A Output Channel [0:15]12
14int16D/A Output Channel [0:15]13
15int16D/A Output Channel [0:15]14
16int16D/A Output Channel [0:15]15
17Reserved
18Reserved
19Reserved
20Reserved
21Reserved
22Reserved
23Reserved
24Reserved
25Reserved
26Reserved
27Reserved
28Reserved
29Reserved
30Reserved
31Reserved
32Reserved
33Reserved
34Reserved
35Ground
36Ground
37Ground
38Ground
39Ground
40Ground
41Ground
42Ground
43Ground
44Ground
45Ground
46Ground
47Ground
48Ground
49Ground
50Ground
51Reserved
52Reserved
53Reserved
54Reserved
55Reserved
56Reserved
57Reserved
58Reserved
59Reserved
60Reserved
61Reserved
62Reserved
63Reserved
64Reserved
65Reserved
66Reserved
67Reserved
68Reserved

Terminal Board

The pin mapping goes with the following terminal board: