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Documentation
CONTENTS

Speedgoat IO397 Analog Input, Analog Output and TTL Interfaces

Speedgoat IO397 Analog Input, Analog Output and TTL Interfaces — Front interfaces with 4 Analog Input, 4 Analog Output and 14 TTL I/O lines

Supported Modules

  • IO397-50k

Analog Input Interface

IO397 AI Data [0:3]

The IO397 I/O module provides 4 simultaneous 16-bit 200 kHz analog input data channels. The corresponding IO397 AI Trigger and IO397 AI Valid must be selected as well.

  • 4 channels

  • Data Type: int16 or uint16

  • Direction: output

DescriptionAnalog Input Voltage (Range ±10.24)Analog Input Voltage (Range ±10)Analog Input Voltage (Range ±5.12)Analog Input Voltage (Range ±5)Digital Code
Full Scale Range (FSR)20.48 V20 V10.24 V10 V-
Least Significant Bit (LSB)312.5 µV305.18 µV156.25 µV152.59 µV-
Full Scale (positive)10.239688 V9.999695 V5.119844 V4.999847 V0x7FFF
FSR - 1 LSB10.239375 V9.999390 V5.119688 V4.999695 V0x7FFE
Mid-scale + 1 LSB312.5 µV305 µV156 µV152.5 µV0x0001
Mid-scale0.0 V 0x0000
Mid-scale - 1 LSB-312.5 µV-305 µV-156 µV-152.5 µV0xFFFF
-FSR + 1 LSB-10.239688 V-9.999695 V-5.119844 V4.999847 V0x8001
Full Scale (negative)-10.24 V-10 V-5.12 V-5V0x8000

DescriptionAnalog Input Voltage (Range +10.24)Analog Input Voltage (Range +10)Analog Input Voltage (Range +5.12)Digital Code
Full Scale Range (FSR)10.24 V10 V5.12 V-
Least Significant Bit (LSB)156.25 µV152.59 µV78.125 µV-
Full Scale (positive)10.24 V10 V5.12 V0xFFFF
FSR - 1 LSB10.239844 V9.999847 V5.119922 V0xFFFE
Mid-scale5.12 V5 V2.56 V0x8000
Zero + 1 LSB156.25 µV152.59 µV78.125 µV0x0001
Zero0.0 V 0x0000

IO397 AI Valid

This mandatory port indicates when the analog input data is valid. The port signal is a single clock pulse of the design under test (DUT) frequency. Since the DUT can be set to run faster than the ADC, there will not necessarily be valid data available at every clock tick.

  • The AI Valid for the corresponding AI Data is mandatory

  • Data Type: boolean

  • Direction: input

IO397 AI Trigger

This mandatory port triggers the conversion of the analog input. Ideally the trigger signal should be implemented as a single clock pulse of the design under test (DUT) frequency.

  • The AI Trigger for the corresponding AI Data is mandatory

  • Data Type: boolean

  • Direction: output

Analog Output Interface

IO397 AO Data [0:3]

The IO397 I/O module provides 4 simultaneous 16-bit 100 kHz analog output channels. The corresponding IO397 AO Trigger must be selected as well.

  • 4 channels

  • Data Type: int16 or uint16

  • Direction: output

DescriptionAnalog Output Voltage (Range ±10)Analog Output Voltage (Range ±5)Digital Code
Full Scale Range (FSR)20 V10 V-
Least Significant Bit (LSB)305 µV152.5 µV-
Full Scale (positive)9.999695 V4.999847 V0x7FFF
FSR - 1 LSB9.999390 V4.999695 V0x7FFE
Mid-scale + 1 LSB305 µV152.5 µV0x0001
Mid-scale0.0 V 0x0000
Mid-scale - 1LSB-305 µV-152.5 µV0xFFFF
-FSR + 1LSB-9.999695 V4.999847 V0x8001
Full Scale (negative)-10 V-5 V0x8000

DescriptionAnalog Output Voltage (Range +10)Analog Output Voltage (Range +5)Digital Code
Full Scale Range (FSR)10 V5 V-
Least Significant Bit (LSB)152.59 µV76.29 µV-
Full Scale (positive)10 V5 V0xFFFF
FSR - 1 LSB9.999847 V4.999923 V0xFFFE
Mid-scale5 V2.5 V0x8000
Zero + 1 LSB152.59 µV78.29 µV0x0001
Zero0.0 V 0x0000

IO397 AO Trigger

This mandatory port triggers the analog outputs. Ideally the trigger signal should be implemented as a single clock pulse of the design under test (DUT) frequency.

  • The AO Trigger for the corresponding AO Datais mandatory

  • Data Type: boolean

  • Direction: output

IO397 AO Ready

This non-mandatory port indicates to the design under test (DUT) that the analog output conversion has completed. When the conversion completes, this signal will go high, to indicate to the DUT that a new data value can be passed to the analog output.

  • The AO Ready for the corresponding AO Data is non-mandatory

  • Data Type: boolean

  • Direction: input

Bidirectional TTL Interface

IO397 TTL [0:13]

This is the input or output signal going to the TTL input or output lines from the DUT.

  • Data Type: boolean

  • Direction: input or output

IO397 TTL Output Enable [0:13]

This is the output enable signal when the corresponding IO397 TTL line is bidirectional.

  • Data Type: boolean

  • Direction: output

Note: Switching from input to output takes three FPGA ticks due to additional logic in the IO397 GPIO FPGA IP core.

Bidirectional Interface Description

Bidirectional signals require both an input buffer and an output buffer with a switchable 3-state driver. The figure below shows the implementation of a bidirectional interface using a generic IOBUF primitive.

  • A logic high ('1') from the Bidirectional Output Enable FPGA-Logic enables the output buffer (3-state is off → I/O pin acts as an output).

    In this situation, the I/O pin will be driven to the same condition as the Bidirectional Output FPGA-Logic.

    The Bidirectional Input FPGA-Logic is the same as the Bidirectional Output FPGA-Logic due to the loopback via the input buffer.

  • A logic low ('0') on the Bidirectional Output Enable FPGA-Logic disables the output buffer (3-state is 'Hi Z' → I/O pin acts as an input).

    In this situation, the condition of the I/O pin is buffered from the input buffer and forwarded to the Bidirectional Input FPGA-Logic. The condition of the Bidirectional Output FPGA-Logic has no effect.

Bidirectional Output EnableBidirectional OutputBidirectional InputI/O Pin
0X= I/O PinZ
1111
1000

Interface Pin Mapping

The pin mapping for the IO397 analog input, analog output and TTL front I/O interfaces is as follows:

Note: 0 V is internally connected to the ground of the target machine whereas analog ground is connected to the ground of the I/O module. 5 V are supplied by the real-time target machine, which is capable of providing 1 A continuous current. For more information, refer to the real-time target machine user manual.

ChannelTerminal PinData TypeTarget Platform InterfacesBit Range Address FPGA Pin
Single-Ended: Analog Input 11A(u)int16

IO397 AI Data

Channel 01 (+)

Differential: Analog Input 1+
Single-Ended: Ground2A(u)int16

IO397 AI Data

Channel 01 (-/ground)

Differential: Analog Input 1-
Single-Ended: Analog Input 23A(u)int16

IO397 AI Data

Channel 02 (+)

Differential: Analog Input 2+
Single-Ended: Ground4A(u)int16

IO397 AI Data

Channel 02 (-/ground)

Differential: Analog Input 2-
Single-Ended: Analog Input 35A(u)int16

IO397 AI Data

Channel 03 (+)

Differential: Analog Input 3+
Single-Ended: Ground6A(u)int16

IO397 AI Data

Channel 03 (-/ground)

Differential: Analog Input 3-
Single-Ended: Analog Input 47A(u)int16

IO397 AI Data

Channel 04 (+)

Differential: Analog Input 4+
Single-Ended: Ground8A(u)int16

IO397 AI Data

Channel 04 (-/ground)

Differential: Analog Input 4-
Analog Output 19A(u)int16

IO397 AO Data

Channel 01

Analog Output 210A(u)int16

IO397 AO Data

Channel 02

Analog Output 311A(u)int16

IO397 AO Data

Channel 03

Analog Output 412A(u)int16

IO397 AO Data

Channel 04

 13AGround
 14AGround
 15A0 V
 16A5 VDC
 17AGround
 1b0 V
 2b5 VDC
Digital I/O 03bbooleanIO397 TTL [0:13]0
Digital I/O 14bbooleanIO397 TTL [0:13]1
Digital I/O 25bbooleanIO397 TTL [0:13]2
Digital I/O 36bbooleanIO397 TTL [0:13]3
Digital I/O 47bbooleanIO397 TTL [0:13]4
Digital I/O 58bbooleanIO397 TTL [0:13]5
Digital I/O 69bbooleanIO397 TTL [0:13]6
Digital I/O 710bbooleanIO397 TTL [0:13]7
Digital I/O 811bbooleanIO397 TTL [0:13]8
Digital I/O 912bbooleanIO397 TTL [0:13]9
Digital I/O 1013bbooleanIO397 TTL [0:13]10
Digital I/O 1114bbooleanIO397 TTL [0:13]11
Digital I/O 1215bbooleanIO397 TTL [0:13]12
Digital I/O 1316bbooleanIO397 TTL [0:13]13
 17bGround

Terminal Board

The pin mapping goes with the following terminal board: