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Documentation
CONTENTS

Speedgoat IO3xx-21 Interface

Speedgoat IO3xx-21 Interface — Rear interface with 56 TTL I/O lines

Supported Modules

  • IO332-200k

  • IO333-325k, IO333-410k, IO333-325k-SFP, IO333-410k-SFP

  • IO334-325k, IO335-325k

  • IO342-1080k, IO342-1450k (only 14 TTL and 2 I2C compatible (bi-directional) I/O lines)

Reference Design Parameters

Select "-21" as your reference design's rear plug-in using the pull-down menu in step 1.2 of the workflow advisor so that the appropriate interfaces will be available in step 1.3 of the workflow.

TTL Interface

TTL IO3xx-21 Channel [0:n]

The IO3xx-21 rear signal conditioning module provides 56 TTL I/O lines. The I/O lines are distributed in 7 groups of 8 lines. All 8 lines of a group must have the same direction and pull resistor configuration. Once the model is generated using HDL Workflow Advisor, the pull resistors of the 7 I/O port groups can be configured using the mask of the generated algorithm block.

  • Supported pull-resistors: pull-up 3.3 V, pull-up 5 V, pull-down, floating

  • Data Type: boolean

  • Direction: input or output

Bidirectional Interface Description

Bidirectional signals require both an input buffer and an output buffer with a switchable 3-state driver. The figure below shows the implementation of a bidirectional interface using a generic IOBUF primitive.

  • A logic high ('1') from the Bidirectional Output Enable FPGA-Logic enables the output buffer (3-state is off → I/O pin acts as an output).

    In this situation, the I/O pin will be driven to the same condition as the Bidirectional Output FPGA-Logic.

    The Bidirectional Input FPGA-Logic is the same as the Bidirectional Output FPGA-Logic due to the loopback via the input buffer.

  • A logic low ('0') on the Bidirectional Output Enable FPGA-Logic disables the output buffer (3-state is 'Hi Z' → I/O pin acts as an input).

    In this situation, the condition of the I/O pin is buffered from the input buffer and forwarded to the Bidirectional Input FPGA-Logic. The condition of the Bidirectional Output FPGA-Logic has no effect.

Bidirectional Output EnableBidirectional OutputBidirectional InputI/O Pin
0X= I/O PinZ
1111
1000

Bidirectional Interface

The IO3xx-21 rear signal conditioning module provides 6 bidirectional TTL I/O lines.

TTL IO3xx-21 Bidirectional Output Enable [0:m]

The inverted value of this port is connected to the T 3-state input port of the IOBUF primitive.

  • Data Type: boolean

  • Direction: output

  • Signal is logic '1': the bidirectional port is acting as output. Signal is logic '0': the bidirectional port is acting as input

TTL IO3xx-21 Bidirectional Output [0:m]

This port is connected to the I (Input) from FPGA Logic port of the IOBUF primitive.

  • Data Type: boolean

  • Direction: output

TTL IO3xx-21 Bidirectional Input [0:m]

This port gets connected to the O (Output) to FPGA Logic port of the IOBUF primitive.

  • Data Type: boolean

  • Direction: input

Interface Pin Mapping

The pin mapping for the IO3xx-21 rear plug-in is as follows:

Terminal PinData TypeTarget Platform InterfacesBit Range Address FPGA PinPort
IO33xIO342 
1booleanTTL IO3xx-21 Channel [0:n]001
2booleanTTL IO3xx-21 Channel [0:n]111
3booleanTTL IO3xx-21 Channel [0:n]2 1
4booleanTTL IO3xx-21 Channel [0:n]3 1
5booleanTTL IO3xx-21 Channel [0:n]4 1
6booleanTTL IO3xx-21 Channel [0:n]5 1
7booleanTTL IO3xx-21 Channel [0:n]6 1
8booleanTTL IO3xx-21 Channel [0:n]7 1
9Ground
10booleanTTL IO3xx-21 Channel [0:n]8 2
11booleanTTL IO3xx-21 Channel [0:n]9 2
12booleanTTL IO3xx-21 Channel [0:n]1022
13booleanTTL IO3xx-21 Channel [0:n]1132
14booleanTTL IO3xx-21 Channel [0:n]12 2
15booleanTTL IO3xx-21 Channel [0:n]13 2
16booleanTTL IO3xx-21 Channel [0:n]14 2
17booleanTTL IO3xx-21 Channel [0:n]15 2
18booleanTTL IO3xx-21 Channel [0:n]1643
19booleanTTL IO3xx-21 Channel [0:n]1753
20booleanTTL IO3xx-21 Channel [0:n]18 3
21booleanTTL IO3xx-21 Channel [0:n]19 3
22booleanTTL IO3xx-21 Channel [0:n]20 3
23booleanTTL IO3xx-21 Channel [0:n]21 3
24booleanTTL IO3xx-21 Channel [0:n]22 3
25booleanTTL IO3xx-21 Channel [0:n]23 3
26Ground
27booleanTTL IO3xx-21 Channel [0:n]2464
28booleanTTL IO3xx-21 Channel [0:n]2574
29booleanTTL IO3xx-21 Channel [0:n]26 4
30booleanTTL IO3xx-21 Channel [0:n]27 4
31booleanTTL IO3xx-21 Channel [0:n]28 4
32booleanTTL IO3xx-21 Channel [0:n]29 4
33booleanTTL IO3xx-21 Channel [0:n]30 4
34booleanTTL IO3xx-21 Channel [0:n]31 4
35booleanTTL IO3xx-21 Channel [0:n]32 5
36booleanTTL IO3xx-21 Channel [0:n]33 5
37booleanTTL IO3xx-21 Channel [0:n]3485
38booleanTTL IO3xx-21 Channel [0:n]3595
39booleanTTL IO3xx-21 Channel [0:n]36 5
40booleanTTL IO3xx-21 Channel [0:n]37 5
41booleanTTL IO3xx-21 Channel [0:n]38 5
42booleanTTL IO3xx-21 Channel [0:n]39 5
43Ground
44booleanTTL IO3xx-21 Channel [0:n]40106
45booleanTTL IO3xx-21 Channel [0:n]41116
46booleanTTL IO3xx-21 Channel [0:n]42 6
47booleanTTL IO3xx-21 Channel [0:n]43 6
48booleanTTL IO3xx-21 Channel [0:n]44 6
49booleanTTL IO3xx-21 Channel [0:n]45 6
50booleanTTL IO3xx-21 Channel [0:n]46 6
51booleanTTL IO3xx-21 Channel [0:n]47 6
52booleanTTL IO3xx-21 Channel [0:n]48 7
53booleanTTL IO3xx-21 Channel [0:n]49 7
54booleanTTL IO3xx-21 Channel [0:n]50127
55booleanTTL IO3xx-21 Channel [0:n]51137
56booleanTTL IO3xx-21 Channel [0:n]52 7
57booleanTTL IO3xx-21 Channel [0:n]53 7
58booleanTTL IO3xx-21 Channel [0:n]54 7
59booleanTTL IO3xx-21 Channel [0:n]55 7
60Ground
61boolean

IO3xx-21 Bidirectional Direction Channel [0:m]

IO3xx-21 Bidirectional Output Channel [0:m]

IO3xx-21 Bidirectional Input Channel [0:m]

0  
62boolean

IO3xx-21 Bidirectional Direction Channel [0:m]

IO3xx-21 Bidirectional Output Channel [0:m]

IO3xx-21 Bidirectional Input Channel [0:m]

1  
63boolean

IO3xx-21 Bidirectional Direction Channel [0:m]

IO3xx-21 Bidirectional Output Channel [0:m]

IO3xx-21 Bidirectional Input Channel [0:m]

20 
64boolean

IO3xx-21 Bidirectional Direction Channel [0:m]

IO3xx-21 Bidirectional Output Channel [0:m]

IO3xx-21 Bidirectional Input Channel [0:m]

31 
65boolean

IO3xx-21 Bidirectional Direction Channel [0:m]

IO3xx-21 Bidirectional Output Channel [0:m]

IO3xx-21 Bidirectional Input Channel [0:m]

4  
66boolean

IO3xx-21 Bidirectional Direction Channel [0:m]

IO3xx-21 Bidirectional Output Channel [0:m]

IO3xx-21 Bidirectional Input Channel [0:m]

5  
67+5 V / 24 mA supply
68+5 V / 24 mA supply

The Interface MSB depends on the I/O Module:

 IO33xIO342
n5513
m51

Terminal Board

The pin mapping goes with the following terminal board: