Speedgoat PCIe Interface
Speedgoat PCIe Interface — Used to read/write data from/to an FPGA
PCIe Interface can be used to read/write data from/to an FPGA
register with a width of up to 32 bits. Use vectorized ports to synchronize PCIe
access of several registers.
PCIe-Read latency: 1.5 µs
PCIe-Write latency: 300 ns
Direction: input or output
Use Cases and Optimizations
Synchronisation:If you would like to
synchronize the write access of multiple registers so that the written
values will be applied on the FPGA at the same time, implement the PCIe
access as a vector of values. Data type conversion may be required as
vectors are only allowed with the same data type. This concept ensures that
there is no time difference compared to when a number of values are written
to the FPGA.
Task Execution Time and Latency:Each PCIe
access, whether it is a write or read access, takes time and can have an
impact on the overall task execution time on the CPU. PCIe write accesses
are only written if the values change compared to the previous sample step.
If the PCIe registers are used as static configuration parameters, which
must be written to the FPGA only once and are not altered during runtime,
these parameters will only be written at the very first sample step and
therefore do not impact the task execution time of the simulation run (note:
the first task execution is treated exceptionally as it makes a longer
execution possible compared to the consecutive sample steps). This concept
is applied on single PCIe access as well as vectorized accesses.
PCIe Read (not implemented on the IO397 I/O
PCIe Read Acceleration:The reading of
register values from the FPGA can have a significant impact on the task
execution time due to significant PCIe latency time. To accelerate the PCIe
read time, a DMA PCIe access is used if the values are read in vectorized
fashion and if the vector holds more than 3 values (with less than 3 values,
the configuration of the DMA access takes more time than if treated as
single PCIe accesses). The figure below illustrates the impact of PCIe
register access on the task execution time of the DMA implementation
compared to when the registers are read as single individual accesses. There
is no further configuration needed for the DMA transfer, as all the settings
are applied automatically if the requirements are met. Refer to the
streaming DMA and DMA from the external DDR RAM for additional information
on fast data transfer to and from the FPGA.
Interface Pin Mapping
There is no interface pin mapping.
This interface does not require a terminal board.