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Documentation
CONTENTS

Speedgoat IO3xx DMA write

Speedgoat IO3xx DMA write — The Speedgoat IO3xx DMA write driver block is used to transfer data with DMA from the CPU to the FPGA

Supported Modules

  • IO332-200k

  • IO333-325k, IO333-410k, IO333-325k-SFP, IO333-410k-SFP

  • IO334-325k

  • IO335-325k

  • IO342-1080k, IO342-1450k

Library

  • >> speedgoatlib_hdlCoder_IO3xx_user

DMA Overview

Direct Memory Access (DMA) is used to reduce the latency of data transferred between the FPGA and the target CPU domain, especially if larger amounts of data need to be transferred. There are different use cases depending on whether the data transfer is in the direction FPGA to CPU (data logging), or in the direction CPU to FPGA (playback) or bidirectional (coprocessor mode). A simplified setup including the basic blocks required to discuss the DMA use cases in a system comprising an FPGA-based I/O module and a Real-Time Target x86 CPU is illustrated below.

The FPGA I/O Module consists of the I/O channels (digital, analog, multi-gigabit transceiver, etc.), the FPGA itself, an external RAM (typically DDR3/DDR4 SDRAM), the design under test (DUT), the DMA engine and the PCIe Endpoint (used to communicate with the Target x86 CPU).

The Motherboard (x86) consists of the Target CPU (x86), the System Memory and the Solid-State Drive (SSD) for persistent data storage.

Description

The DMA write block allows the transfer of data from the CPU into the FPGA RAM domain using an AXI4-Stream interface from the FPGA design under test (DUT) model. Using this stream interface, the data vector presented to the DMA Write block will be translated into the FPGA as a sequence of values. Care should be taken with the FPGA modelling so that values are consumed quickly enough for the given data input vector and model time step. Refer to the examples.

The DMA write interface is an AXI4-Stream INPUT to the DUT design. The required interfaces in the FPGA design are a data input of uint32 data type, a tvalid input of boolean data type, a tlast input of boolean data type and a tready data output of boolean data type that can be used to create backpressure. For more information about the AXI4-Stream interface, refer to the MathWorks Model Design for AXI4-Stream Interface Generation.

Ports

In Ports
data

The Data port supplies data which is streamed from the CPU to the FPGA. The input data type is uint32. The size of the input vector should match the setting for DMA transfer size. The data presented on the input will be transferred into the FPGA DUT model using an AXI Stream interface.

Out Ports
Words Written

This optional data output port, a uint32 value, signifies the number of data values transferred successfully in the active buffer. If modelling and functionality is completing as expected, this value should match the set DMA transfer size . If this value is lower than the set DMA transfer size, the block will continue trying to complete the buffer during the next time step. New buffers are ignored until the present buffer completes.

Parameters

Tab: Engine Setup
FPGA Module Identifier - Unique identifier for FPGA I/O module

1 (default) | n

Enter a unique number. This setting must match the setting of the corresponding design under test (DUT) subsystem generated. This is usually only relevant in a multi-module model, as otherwise the default value 1 is applied. The module identifier ordinal sequence will also correspond to the ordinal sequence of the modules' positions on the PCIe bus. In this way such modules of the same device type can be uniquely identified. For this reason, if multiple modules of the same type are installed in the target machine and one module is not in use within a given model, a bus and slot for the modules which should be used must be specified.

DMA Transfer Size (32 bit words) - Frame size of the DMA transfer

The length of the output port vector (uint32) will be configured according to the transfer size setting.

Polling Enabled

checked | not checked (default)

Use this toggle switch to select polling mode. Polling mode means that one of the CPU cores is dedicated to checking for the completion of the (C)DMA transfer. In this mode, the model execution is triggered when the polling criterion is met. The behavior of the model is identical to a model whose execution is driven by an interrupt, in that the model operates independently of the system timer. This mode will provide the lowest possible latencies and the best performance due to the fact that the latency and time cost of an interrupt service routine are avoided. It is worth noting that depending on the data structure or device being polled, the execution may not be a deterministic process; there could be more jitter in the actual execution time than there would be if the system timer was used. For more details on polling, please consult the MathWorks execution modes documentation. Note that only one block (of any type) may be used for polling, as only one polling function may be registered with Simulink Real Time.

Tab: Status Outputs
Enable Words Written Count

By setting the check-mark as appropriate, the status port described in the ports section can be enabled or disabled.