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Documentation
CONTENTS

Speedgoat IO3xx Setup

Speedgoat IO3xx Setup — The Speedgoat IO3xx setup block performs the setup and configuration to use the Speedgoat IO3xx boards

Library

  • >> speedgoatlib_hdlCoder_IO3xx

Description

This Speedgoat block performs the setup and configuration to use the Speedgoat I/O modules. To use this block, open the HDL Coder HDL Workflow Advisor and use it to generate a Simulink Real-Time interface subsystem. This block is located inside the generated Simulink Real-Time interface subsystem. The mask of this block controls the block parameters. Do not edit the parameters directly. The FPGA I/O module block descriptions are for information purposes only. The relevant parameters are promoted to the top level of the generated Simulink Real-Time interface mask.

Ports

This driver block has no input or output ports.

Parameters

FPGA Model/Subsystem Name - FPGA hierarchical name

character vector

Enter a character vector to identify the model and subsystem containing the Setup block.

FPGA Board Type - Type of FPGA being set up

Select the type of FPGA being set up.

Run FPGA only when Target Application Runs - Startup policy for FPGA

'on' (default) | 'off'

Select this parameter for the FPGA to execute only when the real-time application is running. Clear this parameter for the FPGA to start immediately after the real-time application is loaded.

Dependency:

To enable the Reset FPGA states on start parameter, select this parameter. Note that model execution driven by interrupts from the FPGA requires the FPGA to be started at model load such that the interrupts can be generated. In this case, change the setting to 'off'.

Reset FPGA States on Start - Initial state policy for FPGA

'on' (default) | 'off'

Select this check box for the FPGA to reset the initial state of the FPGA variables and registers to the default state on startup. Clear this check box for the FPGA to retain the end state of the previous execution. To return to the initial state, download the model to the target again and restart the simulation.

Dependency:

To enable this parameter, select Run FPGA only when the target application runs.

Reset FPGA States on Stop - Terminal state policy for FPGA

'on' | 'off' (default)

Select this check box for the FPGA to reset the state of the FPGA variables and registers to the default state at model terminate.

FPGA Module Identifier - Unique identifier for FPGA I/O module

1 (default) | n

Enter a unique number. This setting must match the setting of the corresponding design under test (DUT) subsystem generated. This is usually only relevant in a multi-module model, as otherwise the default value 1 is applied. The module identifier ordinal sequence will also correspond to the ordinal sequence of the modules' positions on the PCIe bus. In this way such modules of the same device type can be uniquely identified. For this reason, if multiple modules of the same type are installed in the target machine and one module is not in use within a given model, a bus and slot for the modules which should be used must be specified.

PCI slot (-1: autosearch) - PCI slot of FPGA I/O module

-1 (default) | [BusNumber, SlotNumber]

Generally, leave the default setting ("-1") to automatically locate the module. If more than one FPGA I/O module is present, and automatic module detection does not function as expected, or especially if there is an unused FPGA module in the target, enter the bus number and the PCI slot number of the module linked to this driver block using the "[BusNumber, SlotNumber]" format.

To determine the PCI bus and slot numbers, type:

>> speedgoat.showInstalledIoModules

Timestamp (*.mcs) - Timestamp as stored in the FPGA programming file

dd/mm/yy hh/mm/ss (read-only)

Displays the timestamp stored in the FPGA programming file (*.mcs).

Bitstream Filename - FPGA programming file

character vector

Enter a character vector to identify the FPGA programming file (*.mcs).

Target Screen Output

This block does not produce any output on the target machine display.