Speedgoat IO334 DMA Streaming Example
Speedgoat IO334 DMA Streaming Example — Example showcasing the use of the Streaming DMA Frame Assembly
The model is called IO334_dma_streaming.slx.
The list of basic software requirements are provided in the prerequisites section of the
Getting Started page.
The IO334 Aurora example uses the following interfaces:
The example uses the following user blocks:
To test the HDL interface functionality, dedicated
examples are included in the downloaded archive file. To open the examples, navigate
to the corresponding folder. Note that the examples only test I/O channels for which
the loopback test method is possible. The terminal board provided must be wired as
described. Examples do not test I/O channels that require external hardware (for
some examples a function generator or an oscilloscope is required), but running this
example will still provide sufficient confirmation of the correct setup of this
implementation. The examples only test interface channels which are provided by the
base functionality of the I/O module. Please note that the examples provided have
been color coded. The green colored subsystem (FPGA domain) is the part of the model
which is actually compiled using HDL Coder and ultimately runs on the FPGA. The FPGA
domain usually has a sample frequency in the range of 100 MHz and is set in the
HDL Workflow Advisor (FPGA Synthesis Software
Settings). The blue blocks (CPU domain) which surround the green
subsystem are interfaces to the processor section of the model. The CPU domain
usually has a sample frequency in the range of 1 kHz. The interrupt subsystem
has been given another color (magenta), as its functionality is asynchronous to both
the processor and FPGA. The interrupt source can be selected in the generated model
in the Interrupt Setup block once the model has been run through the HDL Coder
This example demonstrates the use of the Streaming DMA Frame Assembly block to
stream data from an FPGA-based model to the CPU for data logging. Five sine wave
signals are generated on the FPGA. The signals are streamed to the CPU in frames.
One frame is transferred every CPU time step. On the CPU side, a variant subsystem
is used to unpack the data in desktop simulation mode. The Speedgoat IO3xx DMA Read
block is used to receive the streamed data when the model is deployed to the
real-time target machine. The DMA read interrupt is used to synchronize the CPU with
the incoming data frames from the FPGA. The model configuration block helps to
configure the model for desktop simulation and HDL Code generation or real-time
Open the example model by navigating to the
folder containing the "*.slx" model file and double clicking the file. If the
example is provided as a Simulink Project, navigate to the corresponding example
folder and extract the Simulink project zip file. Then double-click the "*.prj" icon
to open the project. After opening the project, open the model by double clicking
the "*.slx" file. The model is shown as follows:
The DUT_DMA_Streaming subsystem is shown in the following graph. Five sine waves
are generated on the FPGA at a sample rate of 1 μs. The signals are directly
streamed to the CPU using the Speedgoat AXI4-Stream
Interface for accelerated and efficient DMA data streaming.
The Streaming DMA Frame Assembly block handles the data framing. Frames are put
together based on the size of the input vector and the ratio between the FPGA and
CPU model rate. Besides the input signal vector, the block requires a valid signal
which is synchronized with the sine wave generation. All other ports of the
Streaming DMA Frame Assembly block can be directly connected to the AXI4-Stream Interface.
The Interrupt Setup block is used on the top level of the model to synchronize the
CPU model execution with the incoming DMA frames. Select the Speedgoat IO334-325k HDL Coder DMA Read interrupt in the block mask.
In addition, unselect the Run FPGA only when target
application runs option in the IO3xx Setup block located in the
DUT_DMA_Streaming masked subsystem of the generated model. This setting is crucial
to get the FPGA running at the start of the simulation.
This example does not require any external wiring.
Running HDL Workflow Advisor
Before the example can be deployed and run on the real-time target machine, you
will need to run through the HDL Coder Workflow Advisor steps to actually generate
HDL code and a FPGA bitstream using HDL Coder (FPGA Synthesis Software
New: Reference design parameters, set at step 1.2
now control which interfaces will be available to target in step 1.3 of the
workflow. This has reduced the total number of reference designs, and the list of
interfaces available. Please remember to select the front plug-in and rear plug-in
setting that is appropriate for your module, as well as the Aurora settings that
should be used for your model (if applicable). These additional reference design
parameter settings are further described in the interface sections for which they
New: Prior to running the workflow advisor, be
sure to double click the Select Module block in the demo model. If one or more of
your modules support the model (due to available interface compatibility), a pop-up
will display prompting you to select the module you would like to target. If only a
single module is installed, and providing it is compatible, it will be automatically
selected when the box is double clicked.
Upon completion, a newly generated model containing the Simulink Real-Time
interface subsystem appears. At first sight, this subsystem resembles the FPGA
subsystem. However, inside, the Simulink algorithm has been removed and replaced
with blocks that the real-time application will use to communicate with the FPGA
during simulation execution. The newly generated model is now ready to be deployed
to a real-time target machine. To download the FPGA bitstream and the Simulink model
to the target, click the Build Model button on the
Simulink Editor toolbar. The real-time application loads on the Speedgoat target
machine and the FPGA algorithm bitstream loads on the FPGA. If you are using I/O
lines, check that you have connected the lines to the external hardware under test.
Please note that some example models do have Global Delay
Balancing intentionally disabled. If an error is displayed about
delay balancing in step 2.3 of the HDL Coder Workflow Advisor, it can be safely
ignored by checking the Ignore warnings checkbox.
Real-Time Simulation Outputs
The simulation results will be available in the Simulation Data Inspector once the
simulation has completed on the target machine. The following screenshot shows the
streamed sine wave signals. Ensure signal logging is set to frame-based mode if the
simulation results appear different.