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Documentation
CONTENTS

Speedgoat IO333-SFP Video Interface

Speedgoat IO333-SFP Video Interface — Front interface with video input and output

Supported Modules

  • IO333-325k-SFP, IO333-410k-SFP

Video Interface

Axi4-Stream Video - SFP

The IO333-SFP features two SFP ports. They can be used to transfer video streams via multi-gigabit transceivers (MGT). Using different SFP+ Transceivers, the IO333-SFP-video can support one HDMI input and one HDMI output video signal. The interface uses the streaming pixel protocol for AXI4-Stream Video interface mapping.

  • The Master (Video Source) is located on the top of the IO333-SFP

  • The Slave (Video Sink) is located on the bottom of the IO333-SFP

AXI4-Stream Video Interface Generation

With the HDL Coder software, you can implement a simplified pixel stream in your model. The software generates AXI4-Stream Video interfaces in the IP core. The signals of the AXI4-Stream Video interface are described below. Further information on the AXI4-Stream Video interface and its modelling aspects can be found on the following MathWorks documentation page: Model Design for AXI4-Stream Video Interface Generation.

AXI4-Stream Video Signals

To generate a DUT with an AXI4-Stream Video interface, you have to model these two signals:

  • Pixel Data

  • Pixel Control Bus

Pixel Data

The Pixel Data signal is the primary video signal that is transferred across the AXI4-Stream Video interface. It contains the 10-bit 420 Chroma Subsampled color information concatenated to a one-dimensional signal. Cb and Cr share the higher order bytes with each component represented every second pixel. Luminance changes every pixel. Note that the example model contains subsystems showing how to translate this signal into a non-chroma subsampled 444 YCbCr signal (and back to a subsampled signal), which can then be freely changed into other color spaces. These blocks are outside of the HDL Coder portion of the model: they are located in the simulation stimulus creation blocks, are fully HDL synthesizable subsystems, and can be moved into your own models if you prefer to work in another color space.

  • Data Type: ufix24

Bit01234567891011121314151617161920212223
ColorYCb/CrPadding

Pixel Control Bus

The Pixel Control Bus is a Simulink Bus signal with the following signals

hStart

This signal becomes high at the first active pixel of each line.

hEnd

This signal becomes high at the last active pixel of each line.

vStart

This signal becomes high at the first active pixel of a frame.

vEnd

This signal becomes high at the last active pixel of a frame.

Valid

This signal becomes high for each valid pixel.

Ready (optional)

The AXI4-Stream Video interfaces in your DUT can optionally include a Ready signal. In a Slave interface, with the Ready signal, you can apply back pressure. In a Master interface, with the Ready signal, you can respond to back pressure. If you model the Ready signal in your AXI4-Stream Video interfaces, your Master interface must deassert its Valid signal one cycle after the Ready signal is deasserted. If you do not model the Ready signal, the HDL Coder generates the signal and the associated backpressure logic.

Video Status Register

Video Status Register [0:19]

The Video interface provides a status register of the Video IP core for debugging purposes. There is one status register available.

  • Data Type: ufix20

  • Direction: input

BitStatus RegisterStatus BitDefault Value
0Video output locked 1
1Video SynchronizerIdle State1
2Course Align, Wait for VTG SOF 0
3Course Align, Wait for FIFO SOF0
4Fine Align, VTG EOL Leading0
5Fine Align, VTG EOL Lagging0
6Fine Align, VTG SOF Leading0
7Fine Align, VTG SOF Lagging0
8Fine Align Active1
9Fine Align Locked1
10Lost Align, VTG EOL Leading0
11Lost Align, VTG EOL Lagging0
12Lost Align, VTG SOF Leading0
13Align, VTG SOF Lagging0
14Video Timing GeneratorVertical blank locked 1
15Horizontal blank locked1
16Vertical Sync locked0
17Horizontal Sync locked0
18Active Video locked1
19Active Chroma locked1

Note that these signals can be used for diagnostics if, for instance your output signal fails to lock. If this is the case, check your control signaling to ensure that you are generating an output signal with equivalent timing characteristics to the input signal. The output signal must match the input signal's resolution and frame rate. If your output image is scaled and/or cropped, pad the signal to match the characteristics of the input in your model.

SFP Video Pin Mapping

The SFP pin mapping for the IO333-SFP Video Interface is as follows:

ConnectorTarget Platform Interfaces
SFP 1 (top)AXI4-Stream-Video - SFP Master
SFP 2 (bottom)AXI4-Stream-Video - SFP Slave