HDL Workflow Advisor Settings
The pictures shown are for illustrative purposes only, and may not reflect the
correct Vivado tool version and target interface mapping. Only refer to the text for
the correct tool version to set. As a convenience, a new block has been added to the
models: "Select Module". Double clicking this block will allow you to select from
the installed support packages available, and will define the required HDL Coder
Workflow Advisor settings in advance of opening the workflow. Please double-check
the settings as you progress through the workflow.
Launching HDL Workflow Advisor
Right-click on the green subsystem to open the HDL Workflow
Advisor tool.
1.1. Set Target Device and Synthesis Tool
A window will appear. The first step consists of selecting the Target workflow and
platform. For this specific reference design, the following settings in HDL Workflow
Advisor must be set.
Target workflow: Simulink Real-Time FPGA
I/O
Target platform: Select the desired
Simulink-programmable FPGA I/O modules, for example, Speedgoat
IO332-200k
1.2. Set Target Reference Design
In the next step, select the corresponding reference design. Depending on the
number of installed reference designs, different variants of reference designs can
be selected. Note that in past support packages there were a greater number of
target reference designs. Many of these have been condensed by the addition of the
reference design parameters "Front Plugin" and "Rear Plugin". Please be sure to
select these as appropriate for your particular hardware and use case.
Reference design: Please select the desired hardware
combination, for example, Speedgoat IO332-200k
Reference design tool version: Depends on the MATLAB
version
Reference design parameters (if applicable):
PCIe Endpoint: Link Width
X1 - mandatory for Baseline and Mobile real-time target
machines
X2 - for special use cases
X4 - recommended for Performance real-time target
machines
Aurora IP Core: Aurora Mode (Gbps)
Aurora IP Core: Little Endian Support [n:0]
Front Plugin
None - No front plugin is installed (or no front plugin is
being used)
-01LV - Installed module supports this front plugin, which
will be used in the model
-02 - Installed module supports this front plugin, which
will be used in the model
-03 - Installed module supports this front plugin, which
will be used in the model
-04 - Installed module supports this front plugin, which
will be used in the model
-06 - Installed module supports this front plugin, which
will be used in the model
-07 - Installed module supports this front plugin, which
will be used in the model
-08 - Installed module supports this front plugin, which
will be used in the model
Rear Plugin
None - No rear plugin is installed (or no rear plugin is
being used)
-00 - Installed module supports this rear plugin, which
will be used in the model
-21 - Installed module supports this rear plugin, which
will be used in the model
-22 - Installed module supports this rear plugin, which
will be used in the model
1.3. Set Target Interface
The target interfaces are set correctly in the example. When you make changes to
the example you will need to edit the interfaces as appropriate for the style
interface desired for the inputs and outputs of your model. These could be native
interfaces, going to actual pins on the device if I/O modules are available, or they
could be PCIe read or write operations. Several other types of interfaces are also
available for specialized purposes. The example models show interface selections
which are appropriate for the device which your integration package supports. Use
these to assist you with your own work.
1.4. Set Target Frequency
The target frequency defines the base clock rate for your hardware design.
Choosing a clock rate which is too high may cause timing issues. If the synthesize
or implementation tasks of your design fail, this value may be reduced. Generally
100 MHz is a safe choice, however, the choice of some interfaces will require a
clock with a minimum rate.
3.2. Generate RTL Code and IP Core
Until this point HDL Workflow Advisor did not factor in the additional, manually
written HDL code added as Black Box to your model (it simply
focused on the interface and on the code wrapped around your Simulink block). For
more information about the Black Box approach, go to:
Generate Black Box Interface for Subsystem.
To create the VHDL project, you must specify where the Black Box source files are
located. Click Add Source to browse your file
system until you reach the location where the VHDL files are saved. Select all the
files and click Open. The files will appear in the
Additional source files field.
4. Embedded System Integration
HDL Workflow Advisor now has all the information to create the project and build
the FPGA bitstream. If you run through step 4, Workflow Advisor will open Vivado in
the background and generate the bitstream. This can easily take half an hour or
more.
5.2. Generate Simulink Real-Time interface
HDL Workflow Advisor will now generate another test model which is ready to be
built and downloaded to your target. At this point, you can still change the model
configuration as you can do with any other Simulink model. The subsystem has been
replaced by the drivers required to perform PCI read and write access.
Depending on the front and rear plugin, additional function block parameters are
promoted to the top mask. Descriptions of these block parameters are available in
the corresponding Simulink block help documentation (blocks are located inside the
generated subsystem). The base mask parameters are:
-
FPGA Module Identifier - Unique identifier for FPGA I/O
module
1 (default) | n
Enter a unique number. This setting must match the setting of the
corresponding design under test (DUT) subsystem generated. This is
usually only relevant in a multi-module model, as otherwise the default
value 1 is applied. The module identifier ordinal sequence will also
correspond to the ordinal sequence of the modules' positions on the PCIe
bus. In this way such modules of the same device type can be uniquely
identified. For this reason, if multiple modules of the same type are
installed in the target machine and one module is not in use within a given model, a bus and slot for the
modules which should be used must be
specified.
-
PCI slot (-1: autosearch) - PCI slot of FPGA I/O module
-1 (default) | [BusNumber, SlotNumber]
Generally, leave the default setting ("-1") to automatically locate
the module. If more than one FPGA I/O module is present, and automatic
module detection does not function as expected, or especially if there
is an unused FPGA module in the target, enter the bus number and the PCI
slot number of the module linked to this driver block using the
"[BusNumber, SlotNumber]" format.
To determine the PCI bus and slot numbers, type:
>> speedgoat.showInstalledIoModules
-
Sample Time
-1 (default) | scalar
Defines the base sample time at which this driver block gets its
sample hit. This parameter can also be set to -1 for inherited sample
time. The units are in seconds.