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FPGA-Based HIL Testing of Grid-Side Converters

Use an integrated workflow to test grid-tied inverters safely without requiring physical prototypes.

Learn How To

  • Model grid tied converters in Simulink and Simscape
  • Synthesize and validate phase-locked loop (PLL) and current control algorithms
  • Generate HDL code from the inverter model and simulate on an FPGA
  • Stream data from an FPGA to the CPU using direct memory access (DMA)
  • Analyze current ripples in Simulation Data Inspector
  • Test hardware and firmware for all operating conditions

Key Benefits

  • Test grid-tied inverters safely without physical prototypes
  • Reach simulation time steps below 1μs and a resolution of PWM switching signals as low as 4ns
  • Simulate switching dynamics for switching frequencies up to hundreds of kHz in real time
  • Use an integrated workflow from design to real-time testing and verification
  • Ensure compliance of grid code regulations

The Challenges of Grid-Side Converters

Usage of grid-side converters (GSC) has increased with the electrification trend. GSCs are used to interface an AC grid with a DC network. Typical applications are wind and solar power generation, grid-connected electric vehicles, or motor control regenerative drives. GSCs usually combine multiples algorithms such as phase-locked-loop (PLL), cascaded controllers, and pulse-width-modulation (PWM). This complexity can make controllers challenging to test and troubleshoot.

Furthermore, some GSCs need to perform in scenarios such as weak grid conditions, grid harmonics, grid faults, grid outage, and islanding. Such scenarios are difficult and costly to test with a traditional test bench. Hardware-in-the-loop (HIL) testing can speed up and automate the testing process. Compliance with grid code and regulations requires running different operational tests to ensure the safety of the power converter's integration in the grid, for example, to ensure fault ride through.

Grid

Made for SimulinkPassenger Vechiles fixed-wing inverter Electric motor

Solar plant

Wind power

Inverter

Electric motor

Configuration for Real-Time Simulation

Picture_1

Set up a HIL test bench with Simulink and Speedgoat to safely validate power converter controllers without hardware prototypes. This allows you to test all operational conditions, including fault conditions, without risking to damage hardware.

You can test interfaces to the microcontroller such as PWM signals or interfaces with equipment like PLCs through I/O protocols such as PCI, I2C, or EtherCat. With data streaming from an FPGA-based simulation to a CPU, you can analyze current ripples at a resolution lower than 1μs, enabling the validation switching algorithms, debug your system, and analyze power conversion quality. With test scripting and automation, you can automate HIL testing and ensure grid-codes compliance at every design iteration.

Power Electronics Real-Time Simulation with Speedgoat Programmable FPGA

In this example model of a grid-tied inverter, we have a three-phase two-level voltage converter connected to a low voltage grid by an LC filter. A circuit breaker allows to disconnect and connect the converter to the grid. There is a low voltage load on the grid side, and a transformer connects to the medium voltage grid.

By running the closed-loop model on the desktop, you can validate the plant's dynamics and test the control algorithms. Then, to run this model on real-time hardware supporting frequency switching of 20khz, the time steps required will be in the order of microseconds. Achieving these time steps on traditional CPUs is impossible. However, running the plant on an FPGA does meet the time step requirements. By modeling the converter using the sub-cycle averaging method, you can obtain the highest switching frequency dynamics for a given sample time, enabling you to simulate fast dynamics like current ripples.

To run this model on an FPGA, you can go through the Simscape HDL workflow advisor and generate an HDL compatible model from the Simscape network. The obtained HDL subsystem contains a plant model with the converter and the state space representation of the Simscape model generated by the Simscape HDL advisor, running at 1MHz. This plant model is enhanced with high-speed I/Os also running on the FPGA at high frequency. The PWM generation unit generates PWM signals based on the controller outputs at 200Mhz. The PLL and current control are implemented on the CPU, running at 50khz.

A DMA (direct memory access) streaming interface is implemented to stream the FPGA signals to the CPU, where they can then be logged in real-time and displayed in the Simulation Data Inspector (SDI). DMA provides a fast, low latency communication channel between CPU and FPGA.

A bitstream gets generated, and a Simulink FPGA driver block helps to communicate with the FPGA from the host desktop through the target CPU. This allows to tune FPGA parameters via the driver block mask and to inspect data directly in Simulink.

With one click, you can run the simulation on the Speedgoat hardware, interact with the real-time application, and visualize the results in SDI. DMA enables you to stream data from the FPGA to the CPU and achieves a signal resolution of 1ns on the CPU.

The phase voltages and currents are logged in SDI. By zooming, you can see the current ripples with a signal resolution of 1MHz.

 

Picture_4_5

Hardware-in-the-Loop Setup

In this test example, the PWM generation, analog inputs, PWM capture, and analog outputs are mapped to I/O ports of the FPGA. A physical connection (loop-back) is made to connect the analog out and in ports and the PWM generation and PWM capture ports. This connection enables the validation of the system's physical interfaces without deploying the controller to an embedded controller.

For a controller-in-the-loop setup, you can deploy the controller and PWM generation algorithms to a prototype or embedded controller. Simultaneously, the plant model with PWM capture and analog out still runs on the Speedgoat real-time machine, allowing you to test and validate the device under test. 

The Authors

Matthias Schiesser

Matthias Schiesser
FPGA Development Engineer

Manuel Fedou

Manuel Fedou
Senior Application Engineer Electrification


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