The fastest closed-loop sample rates are achieved given the massively parallel nature of FPGAs and because processing can be done entirely on the FPGA itself (eliminating PCIe bus latencies). The CPU can still be used for configuration and monitoring or even in a coprocessing setup involving fast DMA data transfers from and to the FPGA.
Running Simulink® designs on Speedgoat Simulink-programmable FPGA I/O modules using HDL Coder reduces development times and enables you to simulate and verify your algorithm early in the process. This workflow also reduces the number of development cycles on the hardware itself:
- Automatically generate HDL code and synthesize your floating-point or fixed-point Simulink model
- Automatically build and download your real-time application to the FPGA I/O module installed in a Speedgoat target machine
- Run the application in real-time with the click of a button, log data, and monitor and tune parameters
Note that for some Simulink blocks, floating and fixed-point support restrictions may apply. Floating-point support with HDL Coder is ideal for algorithms such as IIR filters, tangents, divisions, and any feedback loops that are difficult to converge. Fixed-point implementations are often more suitable for algorithms such as FIR filters, FFTs, and NCO/mixers.
For more information about software and hardware prerequisites, refer to the software installation and configuration guide.