Fastest closed-loop sample rates leveraging FPGAs can be achieved given the massively parallel nature of FPGAs, and by leveraging FPGA I/O modules providing all required I/O and protocols support through to one or multiple FPGAs with low-latency interconnects, eliminating PCIe bus latencies.
Running Simulink designs on Speedgoat FPGA I/O modules is comparably fast and easy, with no HDL knowledge required:
- Automatically generate HDL code and synthesize your floating-point (available with MATLAB R2016b+) or fixed-point Simulink model
- Automatically build and download your real-time application to the FPGA I/O module either installed in a Speedgoat target machine, or operating on a stand-alone carrier
- Run the application in real-time with the click of a button, log data, monitor and tune parameters
Note that for some Simulink blocks, floating and fixed-point support restrictions may apply. Floating-point support with HDL Coder is ideal for algorithms such as IIR filters, tangents, divisions, and any feedback loop that’s difficult to converge; and fixed-point implementations are oftentimes more suitable for algorithms like FIR filters, FFTs, or NCO/mixers.
For more information about software and hardware prerequisites see the software installation and configuration guide.